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    BARRIER MATERIALS BETWEEN BUMPS AND PADS
    2.
    发明申请
    BARRIER MATERIALS BETWEEN BUMPS AND PADS 审中-公开

    公开(公告)号：WO2019125404A1

    公开(公告)日：2019-06-27

    申请号：PCT/US2017/067227

    申请日：2017-12-19

    Applicant: INTEL CORPORATION

    Inventor： HWANG, Ehren ,  PELTO, Christopher M. ,  SATTIRAJU, Seshu V. ,  GOWRISHANKAR, Shravan ,  ZELL, Zachary A. ,  RAORANE, Digvijay A.

    IPC: H01L21/768

    Abstract: Disclosed are barrier materials between bumps and pads, and related devices and methods. A semiconductor device includes an interconnect, a top material, a pad on the interconnect and at least a portion of the top material, a bump on the pad, and a barrier material between the pad and the bump. The top material defines a via therethrough to the interconnect. The pad includes electrically conductive material. The bump includes electrically conductive material. The bump is configured to electrically connect the interconnect to another device. The barrier material is between the pad and the bump. The barrier material includes a conductive material that is resistant to electromigration, intermetallic compound reaction, or both electromigration and intermetallic compound reaction.

    ELECTROMAGNETIC INTERFERENCE SHIELDING FOR SEMICONDUCTOR PACKAGES USING BOND WIRES
    3.
    发明申请
    ELECTROMAGNETIC INTERFERENCE SHIELDING FOR SEMICONDUCTOR PACKAGES USING BOND WIRES 审中-公开
    半导体封装用粘结线的电磁干扰屏蔽

    公开(公告)号：WO2017171813A1

    公开(公告)日：2017-10-05

    申请号：PCT/US2016/025398

    申请日：2016-03-31

    Applicant: INTEL CORPORATION

    Inventor： RAORANE, Digvijay A. ,  NAIR, Vijay K.

    IPC: H01L23/552 ,  H01L23/48

    Abstract: Electromagnetic interference shielding is described for a semiconductor package using bond wires. In one example, a package has a substrate having a ground plane and a top side to carry a microelectronic die, the top side further having a conductive pad coupled to the ground plane, a microelectronic die having a bottom side attached to the substrate and a top side opposite the bottom side, and a plurality of bond wires connected to the top conductive pad to form a wire mesh electromagnetic interference shield for the substrate.

    Abstract translation: 描述了使用键合线的半导体封装的电磁干扰屏蔽。 在一个示例中，封装具有衬底，衬底具有用于承载微电子管芯的接地平面和顶侧，顶侧进一步具有耦合到接地平面的导电焊盘，具有附接到衬底的底侧的微电子管芯以及 与底面相对的顶面，以及连接到顶部导电焊盘的多个键合线，以形成用于衬底的丝网电磁干扰屏蔽。

    ELECTRONIC PACKAGE ASSEMBLY WITH STIFFENER
    4.
    发明申请
    ELECTRONIC PACKAGE ASSEMBLY WITH STIFFENER 审中-公开

    公开(公告)号：WO2018125251A1

    公开(公告)日：2018-07-05

    申请号：PCT/US2016/069641

    申请日：2016-12-31

    Applicant: INTEL CORPORATION

    Inventor： MALLIK, Debendra ,  RAORANE, Digvijay A.

    IPC: H01L23/16 ,  H01L23/433 ,  H01L25/065

    Abstract: An electronic package technology is disclosed. A first active die can be mountable to and electrically coupleable to a package substrate. A second active die can be disposed on a top side of the first active die, the second active die being electrically coupleable to one or both of the first active die and the package substrate. At least one open space can be available on the top side of the first active die. At least a portion of a stiffener can substantially fill the at least one open space available on the top side of the first active die.

    ENCLOSURE FOR AN ELECTRONIC COMPONENT
    7.
    发明申请
    ENCLOSURE FOR AN ELECTRONIC COMPONENT 审中-公开

    公开(公告)号：WO2019005171A1

    公开(公告)日：2019-01-03

    申请号：PCT/US2017/040517

    申请日：2017-06-30

    Applicant: INTEL CORPORATION

    Inventor： NAIR, Vijay K. ,  RAORANE, Digvijay A.

    IPC: H01L23/31 ,  H01L23/552

    Abstract: Enclosure technology for electronic components is disclosed. An enclosure for an electronic component can comprise a base member and a cover member disposed on the base member such that the cover member and the base member form an enclosure for an electronic component. In one aspect, the base member can have at least one via extending therethrough. The at least one via can be configured to electrically couple an enclosed electronic component with another electronic component external to the enclosure. In another aspect, the cover member can include a protrusion, a receptacle, or both, and the base member can include a mating protrusion, receptacle, or both to facilitate proper alignment of the cover member and the base member. Electronic device packages and associated systems and methods are also disclosed.

    ELECTRONIC PACKAGE ASSEMBLY WITH COMPACT DIE PLACEMENT
    8.
    发明申请
    ELECTRONIC PACKAGE ASSEMBLY WITH COMPACT DIE PLACEMENT 审中-公开

    公开(公告)号：WO2018126258A1

    公开(公告)日：2018-07-05

    申请号：PCT/US2018/012028

    申请日：2018-01-02

    Applicant: INTEL CORPORATION

    Inventor： LI, Eric J. ,  MEHTA, Vipul V. ,  RAORANE, Digvijay A.

    IPC: H01L21/56 ,  H01L25/065

    Abstract: An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.

    STACKING MULTIPLE DIES HAVING DISSIMILAR INTERCONNECT STRUCTURE LAYOUT AND PITCH
    9.
    发明申请
    STACKING MULTIPLE DIES HAVING DISSIMILAR INTERCONNECT STRUCTURE LAYOUT AND PITCH 审中-公开

    公开(公告)号：WO2018125061A1

    公开(公告)日：2018-07-05

    申请号：PCT/US2016/068754

    申请日：2016-12-27

    Applicant: INTEL CORPORATION

    Inventor： RAORANE, Digvijay A. ,  MALLIK, Debendra

    IPC: H01L25/065 ,  H01L23/00

    Abstract: An apparatus is provided comprising: first die, wherein a first plurality of interconnect structures is formed on the first die; one or more layers, wherein a first surface of the one or more layers is attached to the first plurality of interconnect structures; a second plurality of interconnect structures formed on a second surface of the one or more layers; and a second die, wherein a third plurality of interconnect structures is formed on the second die, wherein a first interconnect structure of the first plurality of interconnect structures is electrically connected to a second interconnect structure of the second plurality of interconnect structures through the one or more layers, and wherein the first die is mounted on the second die such that the second interconnect structure of the second plurality of interconnect structures is attached to a third interconnect structure of the third plurality of interconnect structures.

    BRIDGE HUB TILING ARCHITECTURE
    10.
    发明公开
    BRIDGE HUB TILING ARCHITECTURE 审中-公开

    公开(公告)号：EP3506352A1

    公开(公告)日：2019-07-03

    申请号：EP18209345.0

    申请日：2018-11-29

    Applicant: INTEL Corporation

    Inventor： COLLINS, Andrew P. ,  RAORANE, Digvijay A. ,  GOMES, Wilfred ,  MAHAJAN, Ravindranath V. ,  SHARAN, Sujit

    IPC: H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H01L23/48

    Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.

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