公开(公告)号：US11158515B2

公开(公告)日：2021-10-26

申请号：US16334324

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Rahim Kasim ,  Manish Chandhok ,  Florian Gstrein

IPC: H01L21/3213 ,  H01L21/302 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.

公开(公告)号：US11749560B2

公开(公告)日：2023-09-05

申请号：US16141522

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Thomas Marieb ,  Zhiyong Ma ,  Miriam R. Reshotko ,  Christopher Jezewski ,  Flavio Griggio ,  Rahim Kasim ,  Nikholas G. Toledo

IPC: H01L21/768 ,  H01L23/532 ,  C25D3/58 ,  C23C18/48

CPC classification number: H01L21/76802 ,  C23C18/48 ,  C25D3/58 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53223 ,  H01L23/53238

Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

公开(公告)号：US20200098619A1

公开(公告)日：2020-03-26

申请号：US16141522

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Thomas Marieb ,  Zhiyong Ma ,  Miriam R. Reshotko ,  Christopher Jezewski ,  Flavio Griggio ,  Rahim Kasim ,  Nikholas G. Toledo

IPC: H01L21/768 ,  H01L23/532 ,  C23C18/48 ,  C25D3/58

Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

公开(公告)号：US12176214B2

公开(公告)日：2024-12-24

申请号：US17510219

申请日：2021-10-25

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Rahim Kasim ,  Manish Chandhok ,  Florian Gstrein

IPC: H01L21/768 ,  H01L21/302 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.