公开(公告)号：US11552010B2

公开(公告)日：2023-01-10

申请号：US16603863

申请日：2017-05-12

Applicant: Intel Corporation

Inventor： Robert A. May ,  Andrew J. Brown ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta

IPC: H01L23/498 ,  C07D413/12 ,  C08G73/16 ,  C08K3/22 ,  C08K3/38 ,  C08K5/548 ,  C08K13/02 ,  H01L21/48

Abstract: The present disclosure is directed to systems and methods for providing a dielectric layer on a semiconductor substrate capable of supporting very high density interconnects (i.e., ≥100 IO/mm). The dielectric layer includes a maleimide polymer in which a thiol-terminated functional group crosslinks with an epoxy resin. The resultant dielectric material provides a dielectric constant of less than 3 and a dissipation factor of less than 0.001. Additionally, the thiol functional group forms coordination complexes with noble metals present in the conductive structures, thus by controlling the stoichiometry of epoxy to polyimide, the thiol-polyimide may beneficially provide an adhesion enhancer between the dielectric and noble metal conductive structures.

公开(公告)号：US11272619B2

公开(公告)日：2022-03-08

申请号：US16321420

申请日：2016-09-02

Applicant: INTEL CORPORATION

Inventor： Kristof Darmawikarta ,  Robert A. May ,  Yikang Deng ,  Ji Yong Park ,  Maroun D. Moussallem ,  Amruthavalli P. Alur ,  Sri Ranga Sai Boyapati ,  Lilia May

IPC: H05K1/18 ,  H05K3/42 ,  H01L21/60 ,  H01L27/146 ,  G01J5/20 ,  H05K1/11 ,  H05K3/46

Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.

公开(公告)号：US20190198436A1

公开(公告)日：2019-06-27

申请号：US15855453

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L23/498 ,  H01L21/48 ,  H01F27/28 ,  H01F41/04 ,  H01F27/40

CPC classification number: H01L23/49838 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/043 ,  H01F2027/2809 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/16157 ,  H01L2924/19042 ,  H01L2924/19102

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

公开(公告)号：US09842800B2

公开(公告)日：2017-12-12

申请号：US15082844

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Robert A. May

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/49827

Abstract: Methods of forming conductive interconnect structures are described. Those methods/structures may include providing a package substrate comprising a substrate core, and forming at least one conductive interconnect structure disposed on the substrate core. The conductive interconnect structure may comprise a first side that is directly disposed on a surface of the substrate core, and a second side opposite the first side, wherein the second side comprises a greater length than a length of the first side.

公开(公告)号：US20170301619A1

公开(公告)日：2017-10-19

申请号：US15641117

申请日：2017-07-03

Applicant: Intel Corporation

Inventor： Siddharth K. Alur ,  Sri Chaitra J. Chavali ,  Robert A. May ,  Whitney M. Bryks

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/31058 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/53228 ,  H01L23/53295

Abstract: Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at least one of a metal layer or a polymer layer of an integrated circuit die a surface layer that includes an adhesion-functional group, and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a polymer layer, forming the surface layer may include copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a metal layer, forming the surface layer may include forming on the metal layer a self-assembled monolayer that includes amine group terminations. Other embodiments may be described and/or claimed.

公开(公告)号：US20170278780A1

公开(公告)日：2017-09-28

申请号：US15082844

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Robert A. May

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/49827

Abstract: Methods of forming conductive interconnect structures are described. Those methods/structures may include providing a package substrate comprising a substrate core, and forming at least one conductive interconnect structure disposed on the substrate core. The conductive interconnect structure may comprise a first side that is directly disposed on a surface of the substrate core, and a second side opposite the first side, wherein the second side comprises a greater length than a length of the first side.

公开(公告)号：US20170179019A1

公开(公告)日：2017-06-22

申请号：US14972936

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Siddharth K. Alur ,  Sri Chaitra J. Chavali ,  Robert A. May ,  Whitney M. Bryks

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/3105

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/31058 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/53228 ,  H01L23/53295

Abstract: Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at least one of a metal layer or a polymer layer of an integrated circuit die a surface layer that includes an adhesion-functional group, and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a polymer layer, forming the surface layer may include copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a metal layer, forming the surface layer may include forming on the metal layer a self-assembled monolayer that includes amine group terminations. Other embodiments may be described and/or claimed.

公开(公告)号：US12218069B2

公开(公告)日：2025-02-04

申请号：US18091781

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240192453A1

公开(公告)日：2024-06-13

申请号：US18078871

申请日：2022-12-09

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Robert A. May ,  Bai Nie

IPC: G02B6/42

CPC classification number: G02B6/4214

Abstract: An integrated circuit (IC) package substrate comprises an upper surface, a lower surface opposite the upper surface, and an outer side surface extending between the upper surface and the lower surface. At least one optical path is in a plane of the IC package substrate, and at least one vertical optical coupler at an upper or lower surface of the IC package substrate is optically coupled to the optical path.

公开(公告)号：US11574874B2

公开(公告)日：2023-02-07

申请号：US16473598

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Robert A. May ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Srinivas V. Pietambaram ,  Frank Truong ,  Praneeth Akkinepally ,  Andrew J. Brown ,  Lauren A. Link ,  Prithwish Chatterjee

IPC: H01L23/538 ,  H01L21/48

Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.