公开(公告)号：WO2018017348A1

公开(公告)日：2018-01-25

申请号：PCT/US2017/041251

申请日：2017-07-07

Applicant: INTEL CORPORATION

Inventor： SADE, Raanan ,  NUZMAN, Joseph ,  SHWARTSMAN, Stanislav ,  YANOVER, Igor ,  ZUR, Liron

IPC: G06F13/16 ,  G06F12/0811

CPC classification number: G06F12/0815 ,  G06F12/0833 ,  G06F12/0893 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62

Abstract: An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.

Abstract translation: 片上系统（SoC）的示例系统包括处理器，高速缓存和主存储器。 SoC可以包括用于将数据存储在存储器行中的第一存储器，其中存储器行被设置为无效状态。 处理器可以包括耦合到第一存储器的处理器。 处理器可以确定从应用接收的第一数据集的数据大小在数据大小范围内。 处理器可以确定从应用程序接收到的第一数据集合和第二数据集合的集合数据大小至少与存储器行的数据大小相同。 处理器可以执行无效修改（I2M）操作，将存储器行从无效状态更改为修改状态。 处理器可以将第一个数据集和第二个数据集写入内存行。

公开(公告)号：WO2018174933A1

公开(公告)日：2018-09-27

申请号：PCT/US2017/040544

申请日：2017-07-01

Applicant: INTEL CORPORATION

Inventor： VALENTINE, Robert ,  ADELMAN, Menachem ,  GIRKAR, Milind B. ,  SPERBER, Zeev ,  CHARNEY, Mark J. ,  TOLL, Bret L. ,  RAPPOPORT, Rinat ,  CORBAL, Jesus ,  SHWARTSMAN, Stanislav ,  BAUM, Dan ,  YANOVER, Igor ,  HEINECKE, Alexander F. ,  ZIV, Barukh ,  OULD-AHMED-VALL, Elmoustapha ,  GEBIL, Yuri ,  SADE, Raanan

IPC: G06F9/345 ,  G06F9/30

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

公开(公告)号：WO2018174931A1

公开(公告)日：2018-09-27

申请号：PCT/US2017/040541

申请日：2017-07-01

Applicant: INTEL CORPORATION

Inventor： ADELMAN, Menachem ,  VALENTINE, Robert ,  SPERBER, Zeev ,  CHARNEY, Mark J. ,  TOLL, Bret L. ,  RAPPOPORT, Rinat ,  CORBAL, Jesus ,  BAUM, Dan ,  HEINECKE, Alexander F. ,  OULD-AHMED-VALL, Elmoustapha ,  GEBIL, Yuri ,  SADE, Raanan

IPC: G06F9/30

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：WO2018004974A1

公开(公告)日：2018-01-04

申请号：PCT/US2017/035436

申请日：2017-06-01

Applicant: INTEL CORPORATION

Inventor： KLEEN, Andreas ,  SADE, Raanan ,  YASIN, Ahmad ,  RAJWAR, Ravi ,  CHAPPELL, Robert S. ,  DEMENTIEV, Roman

IPC: G06F11/30

CPC classification number: G06F9/30043 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0673 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/3834 ,  G06F11/30 ,  G06F12/0815 ,  G06F12/084

Abstract: A method of analyzing aborts of transactional execution transactions. Starting a transactional execution transaction with a first logical processor. Performing, with a second logical processor, store to memory instructions, while the first logical processor is performing the transactional execution transaction. Capturing memory addresses of, and instruction pointer values associated with, at least a sample of the store to memory instructions. Performing, with the second logical processor, a first store to memory instruction to a first memory address, which is to cause the transactional execution transaction to abort. Capturing the first memory address. Determining an instruction pointer value associated with the first store to memory instruction by correlating at least the captured first memory address with the captured memory addresses of said at least the sample of the store to memory instructions.

Abstract translation:

一种分析事务执行事务异常终止的方法。 用第一个逻辑处理器开始一个事务执行事务。 在第一逻辑处理器正在执行事务执行事务的同时，利用第二逻辑处理器执行对存储器指令的存储。 捕获与存储器的至少一个样本相关联的存储器地址和与存储器指令相关联的指令指针值。 利用第二逻辑处理器执行对存储器指令的第一存储器指令，该第一存储器指令将导致事务执行事务中止。 捕获第一个内存地址。 通过将至少所捕获的第一存储器地址与所述至少所述商店样本的所捕获的存储器地址至存储器指令相关联来确定与所述第一存储器至存储器指令相关联的指令指针值。

公开(公告)号：WO2017112234A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/063211

申请日：2016-11-22

Applicant: INTEL CORPORATION

Inventor： STARK, Tomer ,  GABOR, Ron ,  NUZMAN, Joseph ,  SADE, Raanan ,  BIGBEE, Bryant E.

IPC: G06F12/02 ,  G06F11/07

CPC classification number: G06F11/079 ,  G06F9/38 ,  G06F11/073 ,  G06F11/0751 ,  G06F12/00

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

Abstract translation: 描述与存储器损坏检测有关的方法和设备。 在一个实施例中，硬件处理器包括执行单元和存储器管理单元，所述执行单元执行指令以请求访问存储器的块，所述指针指向存储器的块，以及存储器管理单元， 指针中的存储器损坏检测值用该存储器中用于该块的存储器损坏检测值进行验证，其中指针中存储器损坏检测值的位置可在第一位置和第二不同位置之间选择。

公开(公告)号：WO2013095640A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067217

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  SHALEV, Ron ,  GILAD, Yiftach ,  RAIKIN, Shlomo ,  YANOVER, Igor ,  SHWARTSMAN, Stanislav ,  SADE, Raanan

Inventor： SHALEV, Ron ,  GILAD, Yiftach ,  RAIKIN, Shlomo ,  YANOVER, Igor ,  SHWARTSMAN, Stanislav ,  SADE, Raanan

IPC: G06F13/14 ,  G06F13/38 ,  G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/08 ,  G06F12/0844 ,  G06F12/0897 ,  G06F13/14 ,  G06F13/38

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line. The dataless buffers in such an embodiment being incapable of storing a full cache line and having one or more control bits to indicate state of the respective dataless buffer and an address for an inter-cache transfer line associated with the respective dataless buffer. In such an embodiment, inter-cache transfer logic is to request the inter-cache transfer line from the higher level cache via the data bus and is to further write the inter-cache transfer line into the lower level cache from the data bus.

Abstract translation: 根据本文公开的实施例，提供了用于在分级缓存设计中实现高速缓存之间的有效通信的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有数据总线的集成电路; 与数据总线可通信地接口的低级缓存; 与数据总线可通信地接口的更高级别的缓存; 一个或多个数据缓冲器和一个或多个无数据缓冲器。 这种实施例中的数据缓冲器与数据总线可通信地接口，并且一个或多个数据缓冲器中的每一个具有缓冲存储器以缓冲全高速缓存线，一个或多个控制位以指示各个数据缓冲器的状态，以及 与完整缓存行相关联的地址。 在这种实施例中的无数据缓冲器不能存储完整的高速缓存行并且具有一个或多个控制位以指示相应无数据缓冲器的状态以及与相应无数据缓冲器相关联的高速缓存间传输线的地址。 在这样的实施例中，高速缓存间传输逻辑是经由数据总线从高级缓存请求高速缓存间传输线，并且进一步将数据总线上的缓存间传输线写入低级缓存。

公开(公告)号：WO2013095464A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066630

申请日：2011-12-21

Applicant: INTEL CORPORATION ,  RAIKIN, Shlomo ,  VALENTINE, Robert ,  SADE, Raanan ,  MANDELBLAT, Julius Yuli ,  SHALEV, Ron ,  NOVAKOVSKY, Larisa

Inventor： RAIKIN, Shlomo ,  VALENTINE, Robert ,  SADE, Raanan ,  MANDELBLAT, Julius Yuli ,  SHALEV, Ron ,  NOVAKOVSKY, Larisa

IPC: G06F13/14 ,  G06F13/38 ,  G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/3828 ,  G06F9/3891 ,  G06F12/0891 ,  G06T1/60

Abstract: An apparatus and method are described for efficiently transferring data from a producer core to a consumer core within a central processing unit (CPU). For example, one embodiment of a method comprises: A method for transferring a chunk of data from a producer core of a central processing unit (CPU) to consumer core of the CPU, comprising: writing data to a buffer within the producer core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core; and upon the consumer core detecting that data is available in the cache, providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core.

Abstract translation: 描述了一种用于在中央处理单元（CPU）内有效地将数据从生产者核心传送到消费者核心的装置和方法。 例如，一种方法的一个实施例包括：一种用于将数据块从中央处理单元（CPU）的生产者核心传送到CPU的消费者核心的方法，包括：将数据写入到所述CPU的生产者核心内的缓冲器 CPU直到指定数据量被写入; 在检测到指定量的数据被写入时，响应地产生驱逐周期，使得将数据从填充缓冲器传送到可由生产者核心和消费者核心访问的高速缓存的逐出循环; 并且在消费者核心检测到数据在高速缓存中可用时，在从消费者核心接收到读取信号时从高速缓存提供数据给消费者核心。

公开(公告)号：WO2018048582A1

公开(公告)日：2018-03-15

申请号：PCT/US2017/046812

申请日：2017-08-14

Applicant: INTEL CORPORATION

Inventor： NEIGER, Gilbert ,  PATEL, Baiju V. ,  HILDESHEIM, Gur ,  RAIS, Ron ,  ANDERSON, Andrew V. ,  BRANDT, Jason W. ,  DURHAM, David M. ,  HUNTLEY, Barry E. ,  SADE, Raanan ,  SAHITA, Ravi L. ,  SHANBHOGUE, Vedvyas ,  THIYAGARAJAH, Arumugam

IPC: G06F9/455

CPC classification number: G06F12/1009 ,  G06F9/45545 ,  G06F9/45558 ,  G06F12/1441 ,  G06F12/145 ,  G06F12/1491 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2212/151 ,  G06F2212/651

Abstract: A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.

Abstract translation: 处理系统包括处理核心以执行包括通信地耦合到处理核心的客户操作系统（OS）和存储器管理单元的虚拟机（VM），该VM包括存储设备以存储 包括从与客户OS关联的客户物理地址（GPA）到存储器帧的标识符的映射的扩展页表项（EPTE），与以第一页面模式访问存储器帧关联的第一多个访问权限标志 被由GPA标识的存储器页面的属性引用，以及第二多个访问权限标志与在由GPA标识的存储器页面的属性引用的第二页面模式下访问存储器帧相关联。

公开(公告)号：WO2017172297A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/021108

申请日：2017-03-07

Applicant: INTEL CORPORATION

Inventor： HILDESHEIM, Gur ,  YANOVER, Igor ,  SHWARTSMAN, Stanislav ,  SADE, Raanan ,  RAIS, Ron

IPC: G06F9/30 ,  G06F9/48

Abstract: An apparatus and method are described for at-retirement re-execution of faulting operations. For example, one embodiment of a processor comprises: an out-of-order engine to schedule and dispatch operations to an execution unit at least some of the operations comprising load operations to load data from a system memory and store operations to store data to the system memory; a first circuit to determine whether a current load/store operation is at retirement; a second circuit to cause logging circuitry and/or fault registers to be active when a load/store operation has been dispatched at retirement, wherein upon detection of a fault condition associated with the load/store operation, data associated with the fault is to be written to the logging circuitry and/or fault registers, the second circuit to cause the logging circuitry and/or fault registers to be inactive if the load/store operation has not be dispatched at retirement.

Abstract translation: 描述了用于退役重新执行错误操作的装置和方法。 例如，处理器的一个实施例包括：无序引擎，用于调度和分派操作给执行单元，至少一些操作包括加载操作以加载来自系统存储器的数据并存储操作以将数据存储到 系统内存; 确定当前加载/存储操作是否在退休的第一电路; 第二电路，用于在退役时已经调度加载/存储操作时使得日志记录电路和/或故障寄存器有效，其中在检测到与加载/存储操作相关联的故障状况时，与故障相关联的数据将是 写入记录电路和/或故障寄存器，如果加载/存储操作在退役时未被调度，则第二电路使得记录电路和/或故障寄存器不活动。

公开(公告)号：WO2013095475A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066674

申请日：2011-12-21

Applicant: INTEL CORPORATION ,  RAIKIN, Shlomo ,  SADE, Raanan ,  VALENTINE, Robert ,  MANDELBLAT, Julius Yuli ,  SHALEV, Ron ,  NOVAKOVSKY, Larisa

Inventor： RAIKIN, Shlomo ,  SADE, Raanan ,  VALENTINE, Robert ,  MANDELBLAT, Julius Yuli ,  SHALEV, Ron ,  NOVAKOVSKY, Larisa

IPC: G06F13/14 ,  G06F13/38 ,  G06F9/30

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3881 ,  G06F12/0866 ,  G06F13/1673 ,  G06F13/38 ,  G06T1/20 ,  G06T1/60 ,  G09G5/006

Abstract: An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

Abstract translation: 描述了一种有效地将数据从中央处理单元（CPU）的核心传输到图形处理单元（GPU）的装置和方法。 例如，一种方法的一个实施例包括：将数据写入CPU的核心内的缓冲器，直到指定的数据量被写入为止; 在检测到指定量的数据已被写入时，响应地产生驱逐周期，驱逐循环使数据从缓冲器传送到可由核心和GPU访问的高速缓存; 设置指示以向GPU指示数据在高速缓存中可用; 并且在GPU检测到指示时，在从GPU接收到读取信号时，从高速缓存提供数据给GPU。