公开(公告)号：WO2018204010A1

公开(公告)日：2018-11-08

申请号：PCT/US2018/026127

申请日：2018-04-04

Applicant: INTEL CORPORATION

Inventor： COHEN, Mor M. ,  HADAR, Yaniv ,  SHOOR, Ehud U.

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03949 ,  H04L7/00 ,  H04L7/0004 ,  H04L7/0062 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/03057 ,  H04L25/03146 ,  H04L2201/02 ,  H04L2201/04

Abstract: An apparatus is provided which comprises: a data slicer to receive first data sampled by a data clock; an edge slicer to receive second data sampled by an edge clock; and a Least Mean Square (LMS) circuitry coupled to the data and edge slicers, wherein the LSM circuitry is to generate a code to adjust a phase of one of data clock and/or edge clock relative to one another.