公开(公告)号：US11353900B2

公开(公告)日：2022-06-07

申请号：US16020725

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： Beomseok Choi ,  Siddharth Kulasekaran ,  Krishna Bharath

IPC: G05F1/46 ,  H01L49/02 ,  H02M3/158 ,  H01L25/18

Abstract: An apparatus is provided, where the apparatus includes a first domain including first one or more circuitries, and a second domain including second one or more circuitries. The apparatus may further include a first voltage regulator (VR) to supply power to the first domain from a power bus, a second VR to supply power to the second domain from the power bus, and a third VR coupled between the first and second domains. The third VR may at least one of: transmit power to at least one of the first or second domains, or receive power from at least one of the first or second domains.

公开(公告)号：US11437346B2

公开(公告)日：2022-09-06

申请号：US16025710

申请日：2018-07-02

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Leigh E. Wojewoda ,  Mathew Manusharow ,  Siddharth Kulasekaran

IPC: H01L21/00 ,  H01L23/34 ,  H01L25/065 ,  H01L49/02 ,  H01F27/08 ,  H01L23/64

Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein the inductor is at least partially embedded within the substrate. One or more thermal vent structures extend through at least one of the substrate or a board attached to the substrate. The one or more thermal vent structures provide a thermal pathway for cooling for the inductor.

公开(公告)号：US12224252B2

公开(公告)日：2025-02-11

申请号：US17030121

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  William J. Lambert ,  Haifa Hariri ,  Siddharth Kulasekaran ,  Mathew Manusharow ,  Anne Augustine

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552

Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.

公开(公告)号：US20200006292A1

公开(公告)日：2020-01-02

申请号：US16022515

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  Siddharth Kulasekaran ,  Kaladhar Radhakrishnan

IPC: H01L25/065 ,  H01L25/18 ,  H02M1/08

Abstract: A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.

公开(公告)号：US11710720B2

公开(公告)日：2023-07-25

申请号：US16022515

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  Siddharth Kulasekaran ,  Kaladhar Radhakrishnan

IPC: H01L25/065 ,  H01L25/18 ,  H02M1/08 ,  H02M3/158 ,  H02M1/00

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L25/18 ,  H02M1/08 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H02M1/0009 ,  H02M3/158

Abstract: A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.

公开(公告)号：US20200004282A1

公开(公告)日：2020-01-02

申请号：US16020725

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： Beomseok Choi ,  Siddharth Kulasekaran ,  Krishna Bharath

IPC: G05F1/46 ,  H01L25/18 ,  H02M3/158 ,  H01L49/02

Abstract: An apparatus is provided, where the apparatus includes a first domain including first one or more circuitries, and a second domain including second one or more circuitries. The apparatus may further include a first voltage regulator (VR) to supply power to the first domain from a power bus, a second VR to supply power to the second domain from the power bus, and a third VR coupled between the first and second domains. The third VR may at least one of: transmit power to at least one of the first or second domains, or receive power from at least one of the first or second domains.