公开(公告)号：WO2014004050A2

公开(公告)日：2014-01-03

申请号：PCT/US2013/044799

申请日：2013-06-07

Applicant: INTEL CORPORATION

Inventor： ERMOLAEV, Igor ,  ELMOUSTAPHA, Ould-Ahmed-Vall ,  TOLL, Bret ,  CORBAL, Jesus ,  NARAIKIN, Andrey

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016

Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor a data element shuffle and an operation on the shuffled data elements in response to a single data element shuffle and an operation instruction that includes a destination vector register operand, a first and second source vector register operands, an immediate value, and an opcode are described.

Abstract translation: 用于在计算机处理器中响应于单个数据元素随机播放的数据元素随机播放和对混洗数据元素的操作的系统，装置和方法的实施例，以及包括目的地向量寄存器操作数，第一和第二 描述源向量寄存器操作数，立即值和操作码。

公开(公告)号：WO2012134555A1

公开(公告)日：2012-10-04

申请号：PCT/US2011/063590

申请日：2011-12-06

Applicant: INTEL CORPORATION ,  VALENTINE, Robert, C. ,  HUGHES, Christopher, J. ,  SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  TOLL, Bret ,  GIRKAR, Milind, Baburao ,  FORSYTH, Andrew, Thomas ,  GROCHOWSKI, Edward, Thomas ,  HALL, Jonathan, Cannon

Inventor： VALENTINE, Robert, C. ,  HUGHES, Christopher, J. ,  SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  TOLL, Bret ,  GIRKAR, Milind, Baburao ,  FORSYTH, Andrew, Thomas ,  GROCHOWSKI, Edward, Thomas ,  HALL, Jonathan, Cannon

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/3455 ,  G06F9/355 ,  G06F9/3555 ,  G06F9/383 ,  G06F9/3865

Abstract: Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask

Abstract translation: 描述了用于在计算机处理器中执行收集和散播步幅指令的系统，装置和方法的实施例。 在一些实施例中，收集步幅指令的执行导致根据写入掩码的位值的至少一些位置将条带数据元素从存储器有条件地存储到目的地寄存器中

公开(公告)号：WO2014210363A1

公开(公告)日：2014-12-31

申请号：PCT/US2014/044416

申请日：2014-06-26

Applicant: INTEL CORPORATION

Inventor： HINTON, Glenn ,  TOLL, Bret ,  SINGHAL, Ronak

IPC: G06F9/06 ,  G06F12/08

CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an MxN-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the MxN-bits of the line of memory.

Abstract translation: 处理器包括N位寄存器和用于接收多寄存器存储器访问指令的解码单元。 多寄存器存储器访问指令是指示存储器位置和寄存器。 处理器包括与解码单元和N位寄存器耦合的存储器存取单元。 存储器访问单元响应于多个寄存器存储器访问指令执行多个寄存器存储器存取操作。 该操作涉及在包括指定的寄存器的每个N位寄存器中涉及N位数据。 该操作还涉及与所指示的存储器位置相对应的MxN位的存储器行的不同相应的N位部分。 要在多个寄存器存储器访问操作中涉及的N位寄存器中的N位数据的总位数至少等于存储器行的MxN位的至少一半。

公开(公告)号：WO2019005085A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040152

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： MADDURI, Venkateswara R. ,  OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  CORBAL, Jesus ,  CHARNEY, Mark J. ,  MURRAY, Carl ,  GIRKAR, Milind ,  TOLL, Bret

IPC: G06F9/30 ,  G06F17/10

Abstract: Embodiments of systems, apparatuses, and methods for performing vector-packed controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.

公开(公告)号：WO2019005084A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040150

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： MADDURI, Venkateswara, R. ,  OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  CORBAL, Jesus ,  CHARNEY, Mark, J. ,  MURRAY, Carl ,  GIRKAR, Milind ,  TOLL, Bret

IPC: G06F9/30

Abstract: Embodiments of systems, apparatuses, and methods for vector-packed fractional multiplication of signed words with rounding, saturation, and high-result selection in a processor are described. For example, execution circuitry executes a decoded instruction to perform a fractional multiplication operation for each of a plurality of pairs of packed data elements to yield a plurality of output values, round each of the plurality of output values, detect whether any of the plurality of output values reflect an overflow or underflow, for any of the plurality of output values that reflect an overflow or underflow, saturate the output value, and store the plurality of output values into a corresponding plurality of positions of the packed data destination operand.

公开(公告)号：WO2012134561A1

公开(公告)日：2012-10-04

申请号：PCT/US2011/064487

申请日：2011-12-12

Applicant: INTEL CORPORATION ,  SAN ADRIAN, Jesus Corbal ,  TOLL, Bret ,  VALENTINE, Robert C. ,  GIRKAR, Milind Baburao ,  FORSYTH, Andrew Thomas ,  CHRYSOS, George Z. ,  GROCHOWSKI, Edward Thomas ,  BRADFORD, Dennis ,  WU, Lisa, K. ,  OULD-AHMED-VALL, Elmoustapha

Inventor： SAN ADRIAN, Jesus Corbal ,  TOLL, Bret ,  VALENTINE, Robert C. ,  GIRKAR, Milind Baburao ,  FORSYTH, Andrew Thomas ,  CHRYSOS, George Z. ,  GROCHOWSKI, Edward Thomas ,  BRADFORD, Dennis ,  WU, Lisa, K. ,  OULD-AHMED-VALL, Elmoustapha

IPC: G06F9/30 ,  G06F9/305

CPC classification number: G06F9/324 ,  G06F9/30018 ,  G06F9/30058 ,  G06F9/30094

Abstract: Embodiments of systems, apparatuses, and methods for performing a jump instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a conditional jump to an address of a target instruction when all of bits of a writemask are zero, wherein the address of the target instruction is calculated using an instruction pointer of the instruction and the relative offset.

Abstract translation: 描述了用于在计算机处理器中执行跳转指令的系统，装置和方法的实施例。 在一些实施例中，当写入掩码的所有位都为零时，混合指令的执行导致到目标指令的地址的条件跳转，其中使用指令的指令指针和相对值计算目标指令的地址 抵消。

公开(公告)号：EP3644179A2

公开(公告)日：2020-04-29

申请号：EP19183489.4

申请日：2019-06-28

Applicant: INTEL Corporation

Inventor： HUGHES, Christopher ,  TOLL, Bret ,  HEINECKE, Alexaner ,  BAUM, Dan ,  OULD-AHMED-VALL, ElMoustapha ,  SADE, Raanan ,  VALENTINE, Robert ,  CHARNEY, Mark

IPC: G06F9/30 ,  G06F9/355

Abstract: An apparatus and method for tile-based gather and scatter operations. For example, one embodiment of a processor comprises: a destination tile register to store a 2-D arrangement of data elements; a first source tile register to store indices associated with the data elements; instruction fetch circuitry to fetch a tile gather instruction comprising operands identifying the first source tile register and the destination tile register; a decoder to decode the tile gather instruction; and execution circuitry to determine a plurality of system memory addresses based on the indices from the first source tile register and to load the data elements from the system memory addresses to the destination tile register.

公开(公告)号：EP3644179A3

公开(公告)日：2020-06-03

申请号：EP19183489.4

申请日：2019-06-28

Applicant: INTEL Corporation

Inventor： HUGHES, Christopher ,  TOLL, Bret ,  HEINECKE, Alexaner ,  BAUM, Dan ,  OULD-AHMED-VALL, ElMoustapha ,  SADE, Raanan ,  VALENTINE, Robert ,  CHARNEY, Mark

IPC: G06F9/30 ,  G06F9/355

Abstract: An apparatus and method for tile-based gather and scatter operations. For example, one embodiment of a processor comprises: a destination tile register to store a 2-D arrangement of data elements; a first source tile register to store indices associated with the data elements; instruction fetch circuitry to fetch a tile gather instruction comprising operands identifying the first source tile register and the destination tile register; a decoder to decode the tile gather instruction; and execution circuitry to determine a plurality of system memory addresses based on the indices from the first source tile register and to load the data elements from the system memory addresses to the destination tile register.

公开(公告)号：EP3623940A2

公开(公告)日：2020-03-18

申请号：EP19183497.7

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： HUGHES, Christopher J. ,  TOLL, Bret ,  BAUM, Dan ,  OULD-AHMED-VALL, Elmoustapha ,  SADE, Raanan ,  VALENTINE, Robert ,  CHARNEY, Mark J. ,  HEINECKE, Alexander F.

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to systems and methods for performing instructions specifying horizontal tile operations. In one example, a processor includes fetch circuitry to fetch an instruction specifying a horizontal tile operation, a location of a M by N source matrix comprising K groups of elements, and locations of K destinations, wherein each of the K groups of elements comprises the same number of elements, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction by generating K results, each result being generated by performing the specified horizontal tile operation across every element of a corresponding group of the K groups, and writing each generated result to a corresponding location of the K specified destination locations.

公开(公告)号：EP4141661A1

公开(公告)日：2023-03-01

申请号：EP22200756.9

申请日：2019-06-26

Applicant: Intel Corporation

Inventor： TOLL, Bret ,  HUGHES, Christopher J. ,  BAUM, Dan ,  OULD-AHMED-VALL, Elmoustapha ,  SADE, Raanan ,  VALENTINE, Robert ,  CHARNEY, Mark J. ,  HEINECKE, Alexander F.

IPC: G06F9/30

Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, an apparatus comprises a configuration storage to store configuration information for a two-dimensional (2D) matrix storage, the configuration information to include a first value indicative of a number of rows of the 2D matrix storage and a second value indicative of a number of columns of the 2D matrix storage, fetch circuitry to fetch an instruction, the instruction to specify the 2D matrix storage, a row of the 2D matrix storage, and a 512-bit vector register, decode circuitry, coupled with the fetch circuitry, to decode the instruction, and execution circuitry, coupled with the decode circuitry, to perform operations corresponding to the instruction, including to store the row of the 2D matrix storage to the 512-bit vector register.