公开(公告)号：WO2008074185A1

公开(公告)日：2008-06-26

申请号：PCT/CN2006/003477

申请日：2006-12-19

Applicant: INTEL CORPORATION ,  WANG, Tingqing ,  WANG, Ying

Inventor： WANG, Tingqing ,  WANG, Ying

IPC: H01L21/50 ,  H01L25/10 ,  H01L23/02 ,  H01L23/12

CPC classification number: H01L25/03 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor package (100) may be formed by an embedded package (110) stacked on dies. The embedded package may comprise a first substrate (106) with one or more dies (302,304) attached to one side (132) of the first substrate (106). One or more dies (102,104) may be stacked on the opposite side (134) of the first substrate. The embedded package may be stacked on a die (202,204) mounted on a second substrate (206) with the first substrate coupled to the second substrate at the other side. The entire assembly may be encapsulated.

Abstract translation: 半导体封装（100）可以由堆叠在管芯上的嵌入式封装（110）形成。 嵌入式封装可以包括具有附接到第一衬底（106）的一侧（132）的一个或多个管芯（302,304）的第一衬底（106）。 一个或多个管芯（102,104）可以堆叠在第一衬底的相对侧（134）上。 嵌入式封装可以堆叠在安装在第二衬底（206）上的管芯（202,204）上，其中第一衬底在另一侧耦合到第二衬底。 整个组件可以被封装。

公开(公告)号：WO2019066832A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/053859

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： ZHAO, Junnan ,  WANG, Ying ,  XU, Cheng ,  LEE, Kyu Oh ,  LI, Sheng ,  DENG, Yikang

IPC: H01F27/00 ,  H01F41/00

Abstract: Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.

公开(公告)号：WO2019236229A1

公开(公告)日：2019-12-12

申请号：PCT/US2019/030837

申请日：2019-05-06

Applicant: INTEL CORPORATION

Inventor： BROWN, Andrew James ,  WANG, Ying ,  ZHANG, Chong ,  LINK, Lauren Ashley ,  DENG, Yikang

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/29 ,  H01L23/13 ,  H01L23/00 ,  H01L23/48

Abstract: Disclosed herein are magnetic structures in integrated circuit (1C) package supports, as well as related methods and devices. For example, in some embodiments, an 1C package support may include a conductive line and a magnetic structure around a top surface of the conductive line and side surfaces of the conductive line. The magnetic structure may have a tapered shape that narrows toward the conductive line.

公开(公告)号：EP3803969A1

公开(公告)日：2021-04-14

申请号：EP19816143.2

申请日：2019-05-06

Applicant: Intel Corporation

Inventor： BROWN, Andrew James ,  WANG, Ying ,  ZHANG, Chong ,  LINK, Lauren Ashley ,  DENG, Yikang

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/29 ,  H01L23/13 ,  H01L23/00 ,  H01L23/48

公开(公告)号：EP3506347A1

公开(公告)日：2019-07-03

申请号：EP18209004.3

申请日：2018-11-28

Applicant: INTEL Corporation

Inventor： CHATTERJEE, Prithwish ,  ZHAO, Junnan ,  VADLAMANI, Sai ,  WANG, Ying ,  JAIN, Rahul ,  BROWN, Andrew J. ,  LINK, Lauren A. ,  XU, Cheng ,  LI, Sheng C.

IPC: H01L23/498 ,  H01L21/48

Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.