公开(公告)号：US11442760B2

公开(公告)日：2022-09-13

申请号：US15200725

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Jr-Shian Tsai ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mesut A. Ergin ,  Ravi L. Sahita ,  Andrew J. Herdrich ,  Wei Wang

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/02 ,  G06F12/109 ,  G06F12/10 ,  G11C7/10

Abstract: A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.

公开(公告)号：US20190205737A1

公开(公告)日：2019-07-04

申请号：US15859504

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC: G06N3/063 ,  G06N3/08 ,  G06F7/78 ,  G06T1/20

CPC classification number: G06N3/063 ,  G06F7/78 ,  G06N3/084 ,  G06T1/20

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

公开(公告)号：US09934176B2

公开(公告)日：2018-04-03

申请号：US14582785

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Wei Wang ,  Hsiao-Ping J. Tsai ,  Jongbae Park

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/287 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus for transceiver multiplexing over USB Type-C interconnects is described herein. The apparatus includes a processor, a memory, a USB Type-C connector, a first transmitter, a multiplexed transmitter, a multiplexed receiver, and an on-die inductor. The multiplexed transmitter, when disabled, enables the multiplexed receiver to be in communication over a channel with a second transmitter over the USB Type C connector. The multiplexed receiver, when disabled, enables the multiplexed transmitter to be in communication over the channel with a receiver over the USB Type-C connector. The on-die inductor is disposed in serial with the multiplexed transmitter, and disposed in parallel with the multiplexed receiver. The on-die inductor reduces: effective shunt capacitance and insertion loss between the multiplexed transmitter and the channel; effective shunt capacitance and insertion loss between the channel and the multiplexed receiver.

公开(公告)号：US20240403620A1

公开(公告)日：2024-12-05

申请号：US18679802

申请日：2024-05-31

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC: G06N3/063 ,  G06F7/78 ,  G06F9/00 ,  G06N3/084 ,  G06N20/00 ,  G06T1/20

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

公开(公告)号：US20230053289A1

公开(公告)日：2023-02-16

申请号：US17845794

申请日：2022-06-21

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC: G06N3/063 ,  G06F7/78 ,  G06N3/08 ,  G06N20/00 ,  G06F9/00

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

公开(公告)号：US11412059B2

公开(公告)日：2022-08-09

申请号：US16328865

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Huawei Xie ,  Jun Nakajima ,  David E. Cohen ,  Mesut A. Ergin ,  Wei Wang

IPC: H04L67/568 ,  H04L49/90 ,  G06F9/455

Abstract: Technologies for managing paravirtual network device queue and memory of a network computing device that includes multi-core processor, a multi-layer cache, a host, and a plurality of virtual machine instances. The host is assigned a processor core of the processor and may be configured to copy a received network packet to a last level cache of the multi-layer cache and determine one or more virtual machine instances configured to process the received network packet. Each virtual machine instance has been assigned a processor core of the processor and has been allocated a first level cache of the multi-level cache memory associated with the respective processor core. The host is additionally configured to inject an interrupt into each processor core of the determined virtual machine (s) which indicates to the virtual machine instance (s) that the received network packet is available to be processed.

公开(公告)号：US20180004562A1

公开(公告)日：2018-01-04

申请号：US15200725

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Jr-Shian Tsai ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mesut A. Ergin ,  Ravi L. Sahita ,  Andrew J. Herdrich ,  Wei Wang

IPC: G06F9/455 ,  G06F12/10 ,  G11C7/10

CPC classification number: G06F9/45558 ,  G06F9/3004 ,  G06F9/45533 ,  G06F12/0292 ,  G06F12/10 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2009/45595 ,  G06F2212/151 ,  G11C7/1072

Abstract: A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.

公开(公告)号：US20240338238A1

公开(公告)日：2024-10-10

申请号：US18574849

申请日：2022-01-26

Applicant: Intel Corporation

Inventor： Wei Wang ,  Kun Tian ,  Guang Zeng ,  Gilbert Neiger ,  Rajesh Sankaran ,  Asit Mallick ,  Jr-Shian Tsai ,  Jacob Jun Pan ,  Mesut Ergin

IPC: G06F9/455 ,  G06F9/30

CPC classification number: G06F9/45558 ,  G06F9/3016 ,  G06F9/45545 ,  G06F2009/45579

Abstract: A method and system of host to guest (H2G) notification are disclosed. H2G is provided via an instruction. The instruction is a send user inter-processor interrupt instruction. An exemplary processor includes decoder circuitry to decode a single instruction and execute the decoded single instruction according to the at least the opcode to cause a host to guest notification from a virtual device running in a host machine on the first physical processor to a virtual device driver running on a virtual processor in a guest machine on a second physical processor.

公开(公告)号：US20240289160A1

公开(公告)日：2024-08-29

申请号：US18658822

申请日：2024-05-08

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Jr-Shian Tsai ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mesut A. Ergin ,  Ravi L. Sahita ,  Andrew J. Herdrich ,  Wei Wang

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/02 ,  G06F12/10 ,  G06F12/109 ,  G11C7/10

CPC classification number: G06F9/45558 ,  G06F9/3004 ,  G06F9/45533 ,  G06F12/0292 ,  G06F12/10 ,  G06F12/109 ,  G11C7/1072 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2009/45595 ,  G06F2212/151

Abstract: A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.

公开(公告)号：US12039435B2

公开(公告)日：2024-07-16

申请号：US17845794

申请日：2022-06-21

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC: G06N3/063 ,  G06F7/78 ,  G06F9/00 ,  G06N3/084 ,  G06N20/00 ,  G06T1/20

CPC classification number: G06N3/063 ,  G06F7/78 ,  G06F9/00 ,  G06N3/084 ,  G06N20/00 ,  G06F2207/4824 ,  G06T1/20

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.