公开(公告)号：WO1997021192A1

公开(公告)日：1997-06-12

申请号：PCT/US1996019231

申请日：1996-12-05

Applicant: INTERGRAPH CORPORATION

Inventor： INTERGRAPH CORPORATION ,  KIRKLAND, Dale ,  ALLISON, Cynthia, E. ,  TURNER, James, Paul ,  TERRY, Joseph, Clay ,  FORD, Jeffrey, S.

IPC: G06T01/20

CPC classification number: G06T1/20 ,  G06F15/7864

Abstract: A parallel processing graphics accelerator accelerates graphics rendering devices by being a front-end graphics pre-processor. The accelerator has a plurality of digital signal processors, where each processor has an input in communication with a request bus and an output, and the digital signal processors are arranged in a peer-to-peer configuration so as to process on a cyclical basis each successive graphics request available on a request bus. Related methods are also provided.

Abstract translation: 并行处理图形加速器通过作为前端图形预处理器来加速图形渲染设备。 加速器具有多个数字信号处理器，其中每个处理器具有与请求总线和输出通信的输入，并且数字信号处理器被布置成对等配置，以便以循环的方式处理每个 连续图形请求在请求总线上可用。 还提供了相关方法。

公开(公告)号：EP0867016A1

公开(公告)日：1998-09-30

申请号：EP96942860.0

申请日：1996-12-05

Applicant: Intergraph Corporation

Inventor： KIRKLAND, Dale ,  ALLISON, Cynthia, E. ,  TURNER, James, Paul ,  TERRY, Joseph, Clay ,  FORD, Jeffrey, S.

IPC: G06F15 ,  G06T1

CPC classification number: G06T1/20 ,  G06F15/7864

Abstract: A parallel processing graphics accelerator accelerates graphics rendering devices by being a front-end graphics pre-processor. The accelerator has a plurality of digital signal processors, where each processor has an input in communication with a request bus and an output, and the digital signal processors are arranged in a peer-to-peer configuration so as to process on a cyclical basis each successive graphics request available on a request bus. Related methods are also provided.

公开(公告)号：EP0951670A1

公开(公告)日：1999-10-27

申请号：EP98905953.0

申请日：1998-01-15

Applicant: Intergraph Corporation

Inventor： SHELTON, Gary ,  FARMER, Michael ,  KIRKLAND, Dale

IPC: G06F3 ,  G09B9 ,  G09G5

CPC classification number: G09G5/12 ,  G06F3/1446 ,  G09B9/34

Abstract: A method of synchronizing, at a system frame display rate, a first set of frames displayed by a first monitor with a second set of frames by a second monitor, utilizes frame production rates of the two sets of frames to set the system frame display rate. More particularly, the first set of frames are produced at a first frame production rate by a first graphics engine, and the second set of frames are produced at a second frame production rate by a second graphics engine. The first frame production rate and second frame production rate first are compared to determine which frame production rate is slower. The system frame display rate then is set to be no greater than the slower of the two frame production rates.