公开(公告)号：EP4075131A1

公开(公告)日：2022-10-19

申请号：EP21168769.4

申请日：2021-04-16

Applicant: Imec VZW

Inventor： BARGE, David ,  DU BOIS, Bert ,  SEVERI, Simone ,  RAY CHAUDHURI, Ashesh

IPC: G01N33/487 ,  B81C1/00 ,  B82Y15/00

Abstract: Method for forming a nanopore transistor, comprising:
a. Forming an aperture in a filler material by:
i. providing a fin comprising a semiconductor layer and a top layer;
ii. pattering the top layer to form a pillar;
iii. embedding the pillar in a filler material;
iv. removing the pillar, leaving an aperture;
v. lining the aperture with a spacer material;

b. forming a nanopore by etching through the aperture,
c. Lining the nanopore with a dielectric,
d. Forming a source and a drain by either:
i. Between steps a.ii. and a.iii., doping the bottom semiconductor layer by using the pillar as a mask, or
ii. After step c.,
- filling the aperture with a sealing material, thereby forming a post;
- removing the filler material;
- doping the bottom semiconductor layer by using the post as a mask; and
- removing the sealing material.