公开(公告)号：US20240113053A1

公开(公告)日：2024-04-04

申请号：US18466929

申请日：2023-09-14

Applicant: Infineon Technologies AG

Inventor： Andreas Korzenietz ,  Anton Mauder ,  Christoffer Erbert ,  Julia Zischang

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/05078 ,  H01L2924/13055

Abstract: The application relates to a power semiconductor device, including: a semiconductor body having a front side coupled to a frontside metallization and a backside coupled to a backside metallization; and an active region with a plurality of transistor cells. The frontside metallization includes a first load terminal structure and a control terminal structure. At least one of the first layer and the second layer is laterally segmented, with a first segment being part of the first load terminal structure and a second segment being part of the control terminal structure.

公开(公告)号：US11195713B2

公开(公告)日：2021-12-07

申请号：US16426051

申请日：2019-05-30

Applicant: Infineon Technologies AG

Inventor： Joachim Hirschler ,  Georg Ehrentraut ,  Christoffer Erbert ,  Klaus Goeschl ,  Markus Heinrici ,  Michael Hutzler ,  Wolfgang Koell ,  Stefan Krivec ,  Ingmar Neumann ,  Mathias Plappert ,  Michael Roesner ,  Olaf Storbeck

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L21/18 ,  H01L29/49

Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.

公开(公告)号：US12183696B2

公开(公告)日：2024-12-31

申请号：US18235585

申请日：2023-08-18

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Jens Brandenburg ,  Christoffer Erbert ,  Joachim Hirschler ,  Oliver Humbel ,  Thomas Rupp ,  Carsten Schaeffer ,  Julia Zischang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/485 ,  H01L23/52 ,  H01L23/532

Abstract: A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

公开(公告)号：US11764176B2

公开(公告)日：2023-09-19

申请号：US17400303

申请日：2021-08-12

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Jens Brandenburg ,  Christoffer Erbert ,  Joachim Hirschler ,  Oliver Humbel ,  Thomas Rupp ,  Carsten Schaeffer ,  Julia Zischang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/485 ,  H01L23/53219 ,  H01L23/53233

Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

公开(公告)号：US20230395539A1

公开(公告)日：2023-12-07

申请号：US18235585

申请日：2023-08-18

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Jens Brandenburg ,  Christoffer Erbert ,  Joachim Hirschler ,  Oliver Humbel ,  Thomas Rupp ,  Carsten Schaeffer ,  Julia Zischang

IPC: H01L23/00 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/485 ,  H01L23/53219 ,  H01L23/53233

Abstract: A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

公开(公告)号：US20220059477A1

公开(公告)日：2022-02-24

申请号：US17400303

申请日：2021-08-12

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Jens Brandenburg ,  Christoffer Erbert ,  Joachim Hirschler ,  Oliver Humbel ,  Thomas Rupp ,  Carsten Schaeffer ,  Julia Zischang

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/485

Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

公开(公告)号：US20190385842A1

公开(公告)日：2019-12-19

申请号：US16426051

申请日：2019-05-30

Applicant: Infineon Technologies AG

Inventor： Joachim Hirschler ,  Georg Ehrentraut ,  Christoffer Erbert ,  Klaus Goeschl ,  Markus Heinrici ,  Michael Hutzler ,  Wolfgang Koell ,  Stefan Krivec ,  Ingmar Neumann ,  Mathias Plappert ,  Michael Roesner ,  Olaf Storbeck

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/18 ,  H01L29/49 ,  H01L29/51

Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.