公开(公告)号：US09536585B2

公开(公告)日：2017-01-03

申请号：US14904979

申请日：2014-05-28

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Mengxin Liu ,  Xin Liu ,  Fazhan Zhao ,  Zhengsheng Han

IPC: G11C11/34 ,  G11C11/419

CPC classification number: G11C11/34 ,  G11C11/412 ,  G11C11/419

Abstract: The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed through arranging PMOS transistors and NMOS transistors in series, wherein the part between the drains of a PMOS transistor and an NMOS transistor serves as a storage node; each storage node controls the gate voltage of an NMOS transistor of the other inverter structure and of a PMOS transistor of another inverter structure; a transmission structure consisting of four NMOS transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node. The use of an improved SRAM memory cell based on a DICE structure not only avoids such defects as small static noise margin and being prone to transmission error facing the traditional cell structures consisting of 6 transistors, but also resolves the problem that the current SRAM storage cells based on a DICE structure can easily be affected by the electrical level of storage nodes. This effectively improves reliability of storage cells.

Abstract translation: 本发明提供了一种基于DICE结构的改进的SRAM存储单元，其包括以下结构：通过串联布置PMOS晶体管和NMOS晶体管而形成的四个反相器结构，其中PMOS晶体管的漏极和NMOS晶体管之间的部分用作 存储节点; 每个存储节点控制另一个逆变器结构的NMOS晶体管的栅极电压和另一个反相器结构的PMOS晶体管的栅极电压; 由四个NMOS晶体管组成的传输结构，其源极，栅极和漏极分别与位线/位线条，字线和存储节点连接。 基于DICE结构的改进的SRAM存储单元的使用不仅避免了由6个晶体管组成的传统单元结构面临的小静态噪声容限和易发生传输错误等缺陷，而且解决了当前SRAM存储单元 基于DICE结构可以容易地受到存储节点电平的影响。 这有效地提高了存储单元的可靠性。

公开(公告)号：US20160260474A1

公开(公告)日：2016-09-08

申请号：US14904979

申请日：2014-05-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Mengxin Liu ,  Xin Liu ,  Fazhan Zhao ,  Zhengsheng Han

IPC: G11C11/419

CPC classification number: G11C11/34 ,  G11C11/412 ,  G11C11/419

Abstract: The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed through arranging PMOS transistors and NMOS transistors in series, wherein the part between the drains of a PMOS transistor and an NMOS transistor serves as a storage node; each storage node controls the gate voltage of an NMOS transistor of the other inverter structure and of a PMOS transistor of another inverter structure; a transmission structure consisting of four NMOS transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node. The use of an improved SRAM memory cell based on a DICE structure not only avoids such defects as small static noise margin and being prone to transmission error facing the traditional cell structures consisting of 6 transistors, but also resolves the problem that the current SRAM storage cells based on a DICE structure can easily be affected by the electrical level of storage nodes. This effectively improves reliability of storage cells.

Abstract translation: 本发明提供了一种基于DICE结构的改进的SRAM存储单元，其包括以下结构：通过串联布置PMOS晶体管和NMOS晶体管而形成的四个反相器结构，其中PMOS晶体管的漏极和NMOS晶体管之间的部分用作 存储节点; 每个存储节点控制另一个逆变器结构的NMOS晶体管的栅极电压和另一个反相器结构的PMOS晶体管的栅极电压; 由四个NMOS晶体管组成的传输结构，其源极，栅极和漏极分别与位线/位线条，字线和存储节点连接。 基于DICE结构的改进的SRAM存储单元的使用不仅避免了由6个晶体管组成的传统单元结构面临的小静态噪声容限和易发生传输错误等缺陷，而且解决了当前SRAM存储单元 基于DICE结构可以容易地受到存储节点电平的影响。 这有效地提高了存储单元的可靠性。