公开(公告)号：US08904112B2

公开(公告)日：2014-12-02

申请号：US13843885

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Martin Licht ,  Jonathan Combs ,  Andrew Huang

IPC: G06F12/00 ,  G06F1/32 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F9/3806 ,  G06F9/3814 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

Abstract translation: 这里描述了用于响应于基于历史的使用模式来禁用缓存存储器的方式的方法和装置。 方式预测逻辑是跟踪高速缓存访​​问的方式，并确定是否要禁用某些方式的访问以节省功率，这是基于具有表示预测错过的逻辑状态的功率信号的方式。 与方式计数访问相关联的一个或多个计数器，其中当所述一个或多个计数器之一达到饱和值时，功率信号被设置为表示预测的未命中的逻辑状态。 控制逻辑根据访问方式来调整与一些或多个计数器相关联的方式。

公开(公告)号：US20150089143A1

公开(公告)日：2015-03-26

申请号：US14557474

申请日：2014-12-02

Applicant: Intel Corporation

Inventor： Martin Licht ,  Jonathan Combs ,  Andrew Huang

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F9/3806 ,  G06F9/3814 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

Abstract translation: 这里描述了用于响应于基于历史的使用模式来禁用缓存存储器的方式的方法和装置。 方式预测逻辑是跟踪高速缓存访​​问的方式，并确定是否要禁用某些方式的访问以节省功率，这是基于具有表示预测错过的逻辑状态的功率信号的方式。 与方式计数访问相关联的一个或多个计数器，其中当所述一个或多个计数器之一达到饱和值时，功率信号被设置为表示预测的未命中的逻辑状态。 控制逻辑根据访问方式来调整与一些或多个计数器相关联的方式。

公开(公告)号：US09098284B2

公开(公告)日：2015-08-04

申请号：US14557474

申请日：2014-12-02

Applicant: Intel Corporation

Inventor： Martin Licht ,  Jonathan Combs ,  Andrew Huang

IPC: G06F12/00 ,  G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F9/3806 ,  G06F9/3814 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

Abstract translation: 这里描述了用于响应于基于历史的使用模式来禁用缓存存储器的方式的方法和装置。 方式预测逻辑是跟踪高速缓存访​​问的方式，并确定是否要禁用某些方式的访问以节省功率，这是基于具有表示预测错过的逻辑状态的功率信号的方式。 与方式计数访问相关联的一个或多个计数器，其中当所述一个或多个计数器之一达到饱和值时，功率信号被设置为表示预测的未命中的逻辑状态。 控制逻辑根据访问方式来调整与一些或多个计数器相关联的方式。