公开(公告)号：US08853067B2

公开(公告)日：2014-10-07

申请号：US13957965

申请日：2013-08-02

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Uday Shah ,  Ravi Pillarisetty ,  Been-Yin Jin ,  Marko Radosavljevic ,  Willy Rachmady

IPC: H01L21/3205 ,  H01L29/78 ,  H01L21/762 ,  H01L29/775 ,  H01L29/06 ,  H01L29/66 ,  B82Y99/00

CPC classification number: H01L29/06 ,  B82Y99/00 ,  H01L21/76205 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7854

Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

Abstract translation: 提供了一种方法。 该方法包括在衬底的顶表面上形成多个纳米线并形成与多个纳米线中的每一个的底表面相邻的氧化物层，其中氧化物层将多个纳米线与衬底隔离。

公开(公告)号：US20160064520A1

公开(公告)日：2016-03-03

申请号：US14924643

申请日：2015-10-27

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/66 ,  H01L21/283 ,  H01L21/02 ,  H01L29/15 ,  H01L29/267

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US09219135B2

公开(公告)日：2015-12-22

申请号：US14057204

申请日：2013-10-18

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/775 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L29/778 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US08936974B2

公开(公告)日：2015-01-20

申请号：US14184999

申请日：2014-02-20

Applicant: Intel Corporation

Inventor： Been-Yin Jin ,  Brian S Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/00 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/316

CPC classification number: H01L21/02381 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/31658 ,  H01L21/76283 ,  H01L21/823807 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42324 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.

Abstract translation: 一种提供晶体管或存储单元结构的方法。 该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。