公开(公告)号：US12288789B2

公开(公告)日：2025-04-29

申请号：US18408223

申请日：2024-01-09

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

公开(公告)号：US11908856B2

公开(公告)日：2024-02-20

申请号：US16719257

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/785

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

公开(公告)号：US20230089395A1

公开(公告)日：2023-03-23

申请号：US17448373

申请日：2021-09-22

Applicant: INTEL CORPORATION

Inventor： Benjamin Orr ,  Nicholas A. Thomson ,  Ayan Kar ,  Nathan D. Jack ,  Kalyan C. Kolluru ,  Patrick Morrow ,  Cheng-Ying Huang ,  Charles C. Kuo

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: Integrated circuits including vertical diodes. In an example, a first transistor is above a second transistor. The first transistor includes a first semiconductor body extending laterally from a first source or drain region. The first source or drain region includes one of a p-type dopant or an n-type dopant. The second transistor includes a second semiconductor body extending laterally from a second source or drain region. The second source or drain region includes the other of the p-type dopant or the n-type dopant. The first source or drain region and second source or drain region are at least part of a diode structure, which may have a PN junction (e.g., first and second source/drain regions are merged) or a PIN junction (e.g., first and second source/drain regions are separated by an intrinsic semiconductor layer, or a dielectric layer and the first and second semiconductor bodies are part of the junction).

公开(公告)号：US20240088136A1

公开(公告)日：2024-03-14

申请号：US17943557

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Ayan Kar ,  Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Benjamin Orr

IPC: H01L27/02

CPC classification number: H01L27/027

Abstract: An integrated circuit structure includes a sub-fin, a source region in contact with a first portion of the sub-fin, and a drain region in contact with a second portion of the sub-fin. A body including semiconductor material is above the sub-fin, where the body extends laterally between the source region and the drain region. A gate structure is on the body and includes (i) a gate electrode, and (ii) a gate dielectric between the gate electrode and the body. In an example, a first distance between the drain region and the gate electrode is at least two times a second distance between the source region and the gate electrode, where the first and second distances are measured in a same horizontal plane that runs in a direction parallel to the body. In an example, the body is a nanoribbon, a nanosheet, a nanowire, or a fin.

公开(公告)号：US11837641B2

公开(公告)日：2023-12-05

申请号：US16719281

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC: H01L29/41 ,  H01L29/417 ,  H01L25/18 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L25/18 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/7853 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US11996403B2

公开(公告)日：2024-05-28

申请号：US16713656

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Ting Chang ,  Babak Fallahazad ,  Tanuj Trivedi ,  Jeong Dong Kim ,  Ayan Kar ,  Benjamin Orr

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L29/0673 ,  H01L29/66136

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate.

公开(公告)号：US20240170581A1

公开(公告)日：2024-05-23

申请号：US17992057

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ayan Kar ,  Patrick Morrow ,  Charles C. Kuo ,  Nicholas A. Thomson ,  Benjamin Orr ,  Kalyan C. Kolluru ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/861 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06

CPC classification number: H01L29/8611 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0649

Abstract: An integrated circuit structure includes a sub-fin having at least a first portion that is doped with a first type of dopant, and a second portion that is doped with a second type of dopant. A PN junction is between the first and second portions of the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. A first contact and a second contact comprise conductive material. In an example, the first contact and the second contact are respectively in contact with the first portion and the second portion of the sub-fin. A diode is formed based on the PN junction between the first and second portions, where the first contact is an anode contact of the diode, and the second contact is a cathode contact of the diode.

公开(公告)号：US20240088133A1

公开(公告)日：2024-03-14

申请号：US17943840

申请日：2022-09-13

Applicant: INTEL CORPORATION

Inventor： Nicholas A. Thomson ,  Ayan Kar ,  Kalyan C. Kolluru ,  Mauro J. Kobrinksy ,  Benjamin Orr

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/06 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L23/5283 ,  H01L27/0266 ,  H01L29/0673 ,  H01L29/8611

Abstract: An integrated circuit structure includes a sub-fin having a first type of dopant, a first diffusion region having the first type of dopant and in contact with the sub-fin, and a second diffusion region and a third diffusion region having a second type of dopant and in contact with the sub-fin. The first type of dopant is one of p-type or n-type dopant, and where the second type of dopant is the other of the p-type or n-type dopant. A first body of semiconductor material extends from the second diffusion region to the third diffusion region, and a second body of semiconductor material extends from the first diffusion region towards the second diffusion region. The first diffusion region is a tap diffusion region contacting the sub-fin. In an example, the first diffusion region facilitates formation of a diode for electrostatic discharge (ESD) protection of the integrated circuit structure.

公开(公告)号：US20240088132A1

公开(公告)日：2024-03-14

申请号：US17943819

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Ayan Kar ,  Chu-Hsin Liang ,  Benjamin Orr ,  Biswajeet Guha ,  Brian Greene ,  Chung-Hsun Lin ,  Sabih U. Omar ,  Sameer Jayanta Joglekar

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L29/0673 ,  H01L29/8611

Abstract: An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.

公开(公告)号：US11824116B2

公开(公告)日：2023-11-21

申请号：US16719222

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Ayan Kar ,  Nicholas Thomson ,  Benjamin Orr ,  Nathan Jack ,  Kalyan Kolluru ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7831 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/785

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.