公开(公告)号：US10795853B2

公开(公告)日：2020-10-06

申请号：US15721822

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F1/12 ,  G06F5/06 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US11899615B2

公开(公告)日：2024-02-13

申请号：US18102568

申请日：2023-01-27

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/00 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F1/04 ,  G06F1/12 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

CPC classification number: G06F15/7889 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F9/3869 ,  G06F9/5038 ,  G06F15/167 ,  G06F15/17312

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20230197676A1

公开(公告)日：2023-06-22

申请号：US17557166

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Gerald S. Pasdast ,  Adel A. Elsherbini ,  Nevine Nassif ,  Carleton L. Molnar ,  Vivek Kumar Rajan ,  Peipei Wang ,  Shawna M. Liff ,  Tejpal Singh ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/49838

Abstract: A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die having a first connection to a first serializer/deserializer (SERDES) circuit and a second connection to a second SERDES circuit; a second IC die having the first SERDES circuit; and a third IC die having the second SERDES circuit, in which the first IC die is in a first layer, the second IC die and the third IC die are in a second layer not coplanar with the first layer, the first layer and the second layer are coupled by interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and the first SERDES circuit and the second SERDES circuit are coupled by a conductive pathway.

公开(公告)号：US11294852B2

公开(公告)日：2022-04-05

申请号：US16917888

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20250112204A1

公开(公告)日：2025-04-03

申请号：US18478855

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Julien Sebot ,  Johanna Swan ,  Shawna M. Liff ,  Carleton L. Molnar ,  Tushar Kanti Talukdar

IPC: H01L25/065 ,  G06F12/0811 ,  G06F12/0897 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

Abstract: An embodiment discloses a processor comprising a first die comprising at least one of a processing core or a field programmable gate array, a second die comprising at least a portion of an L1 cache, an L2 cache, or both an L1 cache and an L2 cache, and wherein the first die or the second die is bonded to an adhesive area.

公开(公告)号：US20230187407A1

公开(公告)日：2023-06-15

申请号：US17548304

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Carleton L. Molnar ,  Adel A. Elsherbini ,  Tanay Karnik ,  Shawna M. Liff ,  Robert J. Munoz ,  Julien Sebot ,  Johanna M. Swan ,  Nevine Nassif ,  Gerald S. Pasdast ,  Krishna Bharath ,  Neelam Chandwani ,  Dmitri E. Nikonov

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L24/08 ,  H01L24/20 ,  H01L2224/2101 ,  H01L2224/08147 ,  H01L2924/37001 ,  H01L2924/1427

Abstract: A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

公开(公告)号：US11586579B2

公开(公告)日：2023-02-21

申请号：US17513795

申请日：2021-10-28

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F1/12 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.