公开(公告)号：US20220254090A1

公开(公告)日：2022-08-11

申请号：US17677118

申请日：2022-02-22

Applicant: INTEL CORPORATION

Inventor： Prasoonkumar SURTI ,  Carsten BENTHIN ,  Karthik VAIDYANATHAN ,  Philip LAWS ,  Scott JANUS ,  Sven WOOP

IPC: G06T15/00 ,  G06T15/06

Abstract: Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.

公开(公告)号：US20210350609A1

公开(公告)日：2021-11-11

申请号：US17223395

申请日：2021-04-06

Applicant: Intel Corporation

Inventor： Ingo WALD ,  Gabor LIKTOR ,  Carsten BENTHIN ,  Carson BROWNLEE ,  Johannes GUENTHER ,  Jefferson D. AMSTUTZ

IPC: G06T15/06 ,  G06T15/00

Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.

公开(公告)号：US20200320771A1

公开(公告)日：2020-10-08

申请号：US16786640

申请日：2020-02-10

Applicant: Intel Corporation

Inventor： Sven WOOP ,  Carsten BENTHIN ,  Rasmus BARRINGER ,  Tomas G. AKENINE-MOLLER

IPC: G06T15/06 ,  G06T15/00 ,  G06T15/08

Abstract: Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.

公开(公告)号：US20240282053A1

公开(公告)日：2024-08-22

申请号：US18587800

申请日：2024-02-26

Applicant: Intel Corporation

Inventor： Karthik VAIDYANATHAN ,  Carsten BENTHIN ,  Sven WOOP

IPC: G06T17/10 ,  G06F7/24 ,  G06T1/20 ,  G06T15/00 ,  G06T15/06 ,  G06T15/08 ,  G06T17/20

CPC classification number: G06T17/10 ,  G06F7/24 ,  G06T1/20 ,  G06T15/005 ,  G06T15/06 ,  G06T15/08 ,  G06T17/205

Abstract: Apparatus and method for box-box testing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged BVH nodes; traversal circuitry to traverse query boxes through the BVH, the traversal circuitry to read a BVH node from a top of a BVH node stack and to read a query box from a local storage or memory, the traversal circuitry further comprising: box-box testing circuitry and/or logic to compare maximum and minimum X, Y, and Z coordinates of the BVH node and the query box and to generate an overlap indication if overlap is detected for each of the X, Y, and Z dimensions; distance determination circuitry and/or logic to generate a distance value representing an extent of overlap between the BVH node and the query box; and sorting circuitry and/or logic to sort the BVH node within a set of one or more additional BVH nodes based on the distance value.

公开(公告)号：US20230377267A1

公开(公告)日：2023-11-23

申请号：US17852216

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Lorenzo TESSARI ,  Addis DITTEBRANDT ,  Michael DOYLE ,  Carsten BENTHIN

IPC: G06T17/20 ,  G06T15/00 ,  G06T15/06 ,  G06T1/20

CPC classification number: G06T17/20 ,  G06T15/005 ,  G06T15/06 ,  G06T1/20

Abstract: A method and apparatus for efficiently constructing a bounding volume hierarchy (BVH). For example, one embodiment of an apparatus comprises: a primitive sampler to identify a representative subset of input primitives of a graphics scene; bounding volume hierarchy (BVH) builder hardware logic to construct an approximate BVH based on the representative subset of input primitives; hardware logic to insert input primitives not in the representative subset into leaves of the approximate BVH; and the BVH builder or a different BVH builder to construct a final BVH based on the primitives inserted into the leaves of the approximate BVH.

公开(公告)号：US20230137438A1

公开(公告)日：2023-05-04

申请号：US18090810

申请日：2022-12-29

Applicant: INTEL CORPORATION

Inventor： Karthik VAIDYANATHAN ,  Michael APODACA ,  Thomas RAOUX ,  Carsten BENTHIN ,  Kai XIAO ,  Carson BROWNLEE ,  Joshua BARCZAK

IPC: G06T15/06 ,  G06T1/60

Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

公开(公告)号：US20220157009A1

公开(公告)日：2022-05-19

申请号：US17533341

申请日：2021-11-23

Applicant: INTEL CORPORATION

Inventor： Karthik VAIDYANATHAN ,  Sven WOOP ,  Carsten BENTHIN

IPC: G06T15/06 ,  G06T1/60 ,  G06T9/40 ,  G06T17/00

Abstract: Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; circuitry to traverse one or more of the rays through the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes, wherein the circuitry is to process entries from the top of a first data structure comprising entries each associated with a child node at the current BVH level, the entries being ordered from top to bottom based on a sorted distance of each respective child node.

公开(公告)号：US20210012553A1

公开(公告)日：2021-01-14

申请号：US17032964

申请日：2020-09-25

Applicant: INTEL CORPORATION

Inventor： Michael APODACA ,  Carsten BENTHIN ,  Kai XIAO ,  Carson BROWNLEE ,  Timothy ROWLEY ,  Joshua BARCZAK ,  Travis SCHLUESSLER

IPC: G06T15/06 ,  G06F16/901 ,  G06F7/14 ,  G06F9/38

Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

公开(公告)号：US20240233244A1

公开(公告)日：2024-07-11

申请号：US18413286

申请日：2024-01-16

Applicant: INTEL CORPORATION

Inventor： Scott JANUS ,  Prasoonkumar SURTI ,  Karthik VAIDYANATHAN ,  Alexey SUPIKOV ,  Gabor LIKTOR ,  Carsten BENTHIN ,  Philip LAWS ,  Michael DOYLE

IPC: G06T15/06 ,  G06T1/60 ,  G06T15/00 ,  G06T17/00

CPC classification number: G06T15/06 ,  G06T1/60 ,  G06T15/005 ,  G06T17/005 ,  G06T2210/21

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US20220327763A1

公开(公告)日：2022-10-13

申请号：US17723772

申请日：2022-04-19

Applicant: INTEL CORPORATION

Inventor： Scott JANUS ,  Prasoonkumar SURTI ,  Karthik VAIDYANATHAN ,  Alexey SUPIKOV ,  Gabor LIKTOR ,  Carsten BENTHIN ,  Philip LAWS ,  Michael DOYLE

IPC: G06T15/06 ,  G06T17/00 ,  G06T1/60 ,  G06T15/00

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.