公开(公告)号：US20240071948A1

公开(公告)日：2024-02-29

申请号：US17895112

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Eng Huat GOH ,  Poh Boon KHOO ,  Nurul Khalidah YUSOP ,  Saw Beng TEOH ,  Chan Kim LEE

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/367 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package is provided including: a package substrate with a top surface, wherein the top surface extends to a peripheral side surface of the package substrate; a stiffener with a lateral portion and a basket portion, wherein the lateral portion is positioned over the top surface of the package substrate and the basket portion overhangs from the top surface of the package substrate adjacent to the peripheral side surface of the package substrate; at least one semiconductor die positioned in the basket portion of the stiffener; and at least one wire attached to the at least one semiconductor die and extending out of the basket portion of the stiffener.

公开(公告)号：US20230397333A1

公开(公告)日：2023-12-07

申请号：US17833568

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Chee Kheong YOON ,  Telesphor KAMGAING ,  Jooi Wah WONG ,  Min Suet LIM ,  Kavitha NAGARAJAN ,  Chan Kim LEE ,  Chu Aun LIM

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/115 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09827 ,  H05K2201/0275 ,  H05K2203/107 ,  H05K2203/02 ,  H05K2201/09854

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core. In an embodiment, the core comprises a first sub-core layer and a second sub-core layer. In an embodiment, a via is provided through the first sub-core layer and the second sub-core layer. In an embodiment, the via comprises a first hourglass shape in the first sub-core layer and a second hourglass shape in the second sub-core layer. In an embodiment, a front-side buildup layer is over the core and a backside buildup layer is under the core.