公开(公告)号：US20220139772A1

公开(公告)日：2022-05-05

申请号：US17087523

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Christoper Jezewski ,  Jiun-Ruey Chen ,  Miriam Reshotko ,  James M. Blackwell ,  Matthew Metz ,  Che-Yun Lin

IPC: H01L21/768 ,  H01L27/06

Abstract: Integrated circuit interconnect structures including an interconnect metallization feature with a liner material of a greater thickness between a fill metal and dielectric material, and of a lesser thickness between the fill metal and a lower-level interconnect metallization feature. The liner material may be substantially absent from an interface between the fill metal and the lower-level interconnect metallization feature. Liner material of reduced thickness at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive liner material that may enhance the scalability of interconnect structures. In some embodiments, liner material is deposited upon dielectric surfaces with an area selective atomic layer deposition process. For single damascene implementations, both a via and a metal line may include a selectively deposited liner material.