公开(公告)号：US11886884B2

公开(公告)日：2024-01-30

申请号：US16680907

申请日：2019-11-12

Applicant: Intel Corporation

Inventor： Christopher Wilkerson ,  Binh Pham ,  Patrick Lu ,  Jared Warner Stark, IV

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/3004 ,  G06F9/30058

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

公开(公告)号：US09710391B2

公开(公告)日：2017-07-18

申请号：US13886467

申请日：2013-05-03

Applicant: Intel Corporation

Inventor： Wei Liu ,  Youfeng Wu ,  Christopher Wilkerson ,  Herbert Hum

IPC: G06F15/00 ,  G06F12/0888 ,  G06F9/45 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F12/0888 ,  G06F8/4442 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/383 ,  Y02D10/13

Abstract: Various embodiments of the invention concern methods and apparatuses for power and time efficient load handling. A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store buffer, data cache, or elsewhere. Consequently, accesses to cache are reduced, through direct loading from load value buffers and store buffers, thereby efficiently processing the loads.

公开(公告)号：US20230350814A1

公开(公告)日：2023-11-02

申请号：US18078762

申请日：2022-12-09

Applicant: Intel Corporation

Inventor： Thomas Unterluggauer ,  Fangfei Liu ,  Carlos Rozas ,  Scott Constable ,  Gilles Pokam ,  Francis McKeen ,  Christopher Wilkerson ,  Erik Hallnor

IPC: G06F12/14 ,  G06F12/0815 ,  G06F12/121

CPC classification number: G06F12/1408 ,  G06F12/0815 ,  G06F12/121 ,  G06F2212/1052

Abstract: Techniques and mechanisms for a victim cache to operate in conjunction with another cache to help mitigate the risk of a side-channel attack. In an embodiment, a first line is evicted from a primary cache, and moved to a victim cache, based on a message indicating that a second line is to be stored to the primary cache. The victim cache is accessed using an independently randomized mapping. Subsequently, a request to access the first line results in a search of the victim cache and the primary cache. Based on the search, the first line is evicted from the victim cache, and reinserted in the primary cache. In another embodiment, reinsertion of the first line in the primary cache includes the first line and a third line being swapped between the primary cache and the victim cache.

公开(公告)号：US20200081718A1

公开(公告)日：2020-03-12

申请号：US16680907

申请日：2019-11-12

Applicant: Intel Corporation

Inventor： Christopher Wilkerson ,  Binh Pham ,  Patrick Lu ,  Jared Warner Stark, IV

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

公开(公告)号：US10528473B2

公开(公告)日：2020-01-07

申请号：US15621401

申请日：2017-06-13

Applicant: Intel Corporation

Inventor： Christopher Wilkerson ,  Muhammad M. Khellah ,  Vivek De ,  Ming Zhang ,  Jaume Abella ,  Javier Carretero Casado ,  Pedro Chaparro Monferrer ,  Xavier Vera ,  Antonio Gonzalez

IPC: G06F12/00 ,  G06F12/0864 ,  G06F12/0804 ,  G06F1/3234

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

公开(公告)号：US10521236B2

公开(公告)日：2019-12-31

申请号：US15940408

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Christopher Wilkerson ,  Binh Pham ,  Patrick Lu ,  Jared Warner Stark, IV

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.