公开(公告)号：US11322504B2

公开(公告)日：2022-05-03

申请号：US16021019

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Uygar Avci ,  Daniel Morris ,  Seiyon Kim ,  Yih Wang ,  Ruth Brain ,  Ian Young

IPC: H01L27/11502 ,  H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311

Abstract: Embodiments include a memory array and a method of forming the memory array. A memory array includes a first dielectric over first metal traces, where first metal traces extend along a first direction, second metal traces on the first dielectric, where second metal traces extend along a second direction perpendicular to the first direction, and third metal traces on the second dielectric, where third metal traces extend along the first direction. The memory array includes a ferroelectric capacitor positioned in a trench having sidewalls and bottom surface, where the trench has a depth defined from a top surface of first metal trace to the top surface of third metal trace. The memory array further includes an insulating sidewall, a first electrode, a ferroelectric, and a second electrode disposed in the trench, where the trench has a rectangular cylinder shape defined by the first, second, and third metal traces.

公开(公告)号：US10749104B2

公开(公告)日：2020-08-18

申请号：US16217807

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Daniel Morris ,  Tanay Karnik ,  Sasikanth Manipatruni ,  Kaushik Vaidyanathan ,  Ian Young

IPC: H01L43/02 ,  H03K19/18 ,  H01L27/22 ,  H01L43/10

Abstract: Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.

公开(公告)号：US11411172B2

公开(公告)日：2022-08-09

申请号：US16130912

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Daniel Morris ,  Kaushik Vaidyanathan ,  Tanay Karnik ,  Ian Young

IPC: G11C11/00 ,  H01L43/04 ,  H01L43/06 ,  G11C11/16 ,  G11C11/18 ,  H01L43/10

Abstract: An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.

公开(公告)号：US11723188B2

公开(公告)日：2023-08-08

申请号：US16024578

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Uygar Avci ,  Ian Young ,  Daniel Morris ,  Seiyon Kim ,  Yih Wang ,  Ruth Brain

IPC: H01L23/522 ,  H01L21/768 ,  H10B12/00 ,  H01L49/02

CPC classification number: H10B12/315 ,  H01L21/76808 ,  H01L21/76843 ,  H01L23/5226 ,  H01L28/91 ,  H10B12/033 ,  H10B12/50

Abstract: Embodiments include an embedded dynamic random access memory (DRAM) device, a method of forming an embedded DRAM device, and a memory device. An embedded DRAM device includes a dielectric having a logic area and a memory area, and a trace and a via disposed in the logic area of dielectric. The embedded DRAM device further includes ferroelectric capacitors disposed in the memory area of dielectric, where each ferroelectric capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and where the ferroelectric layer surrounds the first electrode of each ferroelectric capacitor and extends along a top surface of the dielectric in the memory area. The embedded DRAM device includes an etch stop layer above the dielectric. The second etch stop in the logic area may have a z-height that is approximately equal to a z-height of a top surface of the second etch stop in the memory area.

公开(公告)号：US11387404B2

公开(公告)日：2022-07-12

申请号：US16130905

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Tanay Karnik ,  Sasikanth Manipatruni ,  Daniel Morris ,  Kaushik Vaidyanathan ,  Ian Young

IPC: G11C11/00 ,  H01L43/02 ,  H01L43/10 ,  H01L43/06 ,  G11C11/16 ,  G11C11/18

Abstract: An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.