公开(公告)号：US10922227B2

公开(公告)日：2021-02-16

申请号：US16114593

申请日：2018-08-28

Applicant: Intel Corporation

Inventor： Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M Cimini ,  Abhishek R. Appu

IPC: G06F12/08 ,  G06F12/0808 ,  G06F9/38 ,  G06T1/20 ,  G06F12/0815 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0897

Abstract: Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.

公开(公告)号：US20190095327A1

公开(公告)日：2019-03-28

申请号：US16114593

申请日：2018-08-28

Applicant: Intel Corporation

Inventor： Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M Cimini ,  Abhishek R. Appu

IPC: G06F12/0808 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0897 ,  G06F12/0831 ,  G06T1/20 ,  G06F12/0891 ,  G06F12/0815

Abstract: Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.

公开(公告)号：US20180285266A1

公开(公告)日：2018-10-04

申请号：US15477011

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M Cimini ,  Abhishek R. Appu

IPC: G06F12/0808 ,  G06F9/38 ,  G06T1/20 ,  G06F12/0815 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0897

Abstract: Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.

公开(公告)号：US10089230B1

公开(公告)日：2018-10-02

申请号：US15477011

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M Cimini ,  Abhishek R. Appu

IPC: G06F12/08 ,  G06F12/0808 ,  G06F9/38 ,  G06T1/20 ,  G06F12/0815 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0897

Abstract: Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.