公开(公告)号：US20220309349A1

公开(公告)日：2022-09-29

申请号：US17839010

申请日：2022-06-13

Applicant: Intel Corporation

Inventor： Meenakshi Arunachalam ,  Arun Tejusve Raghunath Rajan ,  Deepthi Karkada ,  Adam Procter ,  Vikram Saletore

IPC: G06N3/08 ,  G06F1/3203 ,  G06K9/62 ,  G06F1/324 ,  G06N3/063 ,  G06F1/3206 ,  G06N3/04 ,  G06V10/94

Abstract: Methods, apparatus, systems and articles of manufacture for distributed training of a neural network are disclosed. An example apparatus includes a neural network trainer to select a plurality of training data items from a training data set based on a toggle rate of each item in the training data set. A neural network parameter memory is to store neural network training parameters. A neural network processor is to generate training data results from distributed training over multiple nodes of the neural network using the selected training data items and the neural network training parameters. The neural network trainer is to synchronize the training data results and to update the neural network training parameters.

公开(公告)号：US11029971B2

公开(公告)日：2021-06-08

申请号：US16259608

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Meenakshi Arunachalam ,  Kushal Datta ,  Vikram Saletore ,  Vishal Verma ,  Deepthi Karkada ,  Vamsi Sripathi ,  Rahul Khanna ,  Mohan Kumar

IPC: G06F1/24 ,  G06F9/00 ,  G06F9/445 ,  G06N5/04 ,  G06N3/04 ,  G06F9/50

Abstract: Systems, apparatuses and methods may provide for technology that identifies a first set of compute nodes and a second set of compute nodes, wherein the first set of compute nodes execute more slowly than the second set of compute nodes. The technology may also automatically determine a compute node configuration that results in a relatively low difference in completion time between the first set of compute nodes and the second set of compute nodes with respect to a neural network workload. In an example, the technology applies the compute node configuration to an execution of the neural network workload on one or more nodes in the first set of compute nodes and one or more nodes in the second set of compute nodes.

公开(公告)号：US10922610B2

公开(公告)日：2021-02-16

申请号：US15704668

申请日：2017-09-14

Applicant: Intel Corporation

Inventor： Adam Procter ,  Vikram Saletore ,  Deepthi Karkada ,  Meenakshi Arunachalam

IPC: G06N3/08 ,  G06N20/00

Abstract: Systems, apparatuses and methods may provide for technology that conducts a first timing measurement of a blockage timing of a first window of the training of the neural network. The blockage timing measures a time that processing is impeded at layers of the neural network during the first window of the training due to synchronization of one or more synchronizing parameters of the layers. Based upon the first timing measurement, the technology is to determine whether to modify a synchronization barrier policy to include a synchronization barrier to impede synchronization of one or more synchronizing parameters of one of the layers during a second window of the training. The technology is further to impede the synchronization of the one or more synchronizing parameters of the one of the layers during the second window if the synchronization barrier policy is modified to include the synchronization barrier.

公开(公告)号：US20190155620A1

公开(公告)日：2019-05-23

申请号：US16259608

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Meenakshi Arunachalam ,  Kushal Datta ,  Vikram Saletore ,  Vishal Verma ,  Deepthi Karkada ,  Vamsi Sripathi ,  Rahul Khanna ,  Mohan Kumar

IPC: G06F9/445 ,  G06F9/50 ,  G06N3/04 ,  G06N5/04

Abstract: Systems, apparatuses and methods may provide for technology that identifies a first set of compute nodes and a second set of compute nodes, wherein the first set of compute nodes execute more slowly than the second set of compute nodes. The technology may also automatically determine a compute node configuration that results in a relatively low difference in completion time between the first set of compute nodes and the second set of compute nodes with respect to a neural network workload. In an example, the technology applies the compute node configuration to an execution of the neural network workload on one or more nodes in the first set of compute nodes and one or more nodes in the second set of compute nodes.

公开(公告)号：US11966843B2

公开(公告)日：2024-04-23

申请号：US17839010

申请日：2022-06-13

Applicant: Intel Corporation

Inventor： Meenakshi Arunachalam ,  Arun Tejusve Raghunath Rajan ,  Deepthi Karkada ,  Adam Procter ,  Vikram Saletore

IPC: G06N3/08 ,  G06F1/3203 ,  G06F1/3206 ,  G06F18/214 ,  G06N3/063 ,  G06V10/774 ,  G06V10/82 ,  G06V10/94 ,  G06N3/048

CPC classification number: G06N3/08 ,  G06F1/3203 ,  G06F1/3206 ,  G06F18/214 ,  G06N3/063 ,  G06V10/774 ,  G06V10/82 ,  G06V10/94 ,  G06N3/048

Abstract: Methods, apparatus, systems and articles of manufacture for distributed training of a neural network are disclosed. An example apparatus includes a neural network trainer to select a plurality of training data items from a training data set based on a toggle rate of each item in the training data set. A neural network parameter memory is to store neural network training parameters. A neural network processor is to generate training data results from distributed training over multiple nodes of the neural network using the selected training data items and the neural network training parameters. The neural network trainer is to synchronize the training data results and to update the neural network training parameters.

公开(公告)号：US20190080233A1

公开(公告)日：2019-03-14

申请号：US15704668

申请日：2017-09-14

Applicant: Intel Corporation

Inventor： Adam Procter ,  Vikram Saletore ,  Deepthi Karkada ,  Meenakshi Arunachalam

IPC: G06N3/08 ,  G06F15/18

Abstract: Systems, apparatuses and methods may provide for technology that conducts a first timing measurement of a blockage timing of a first window of the training of the neural network. The blockage timing measures a time that processing is impeded at layers of the neural network during the first window of the training due to synchronization of one or more synchronizing parameters of the layers. Based upon the first timing measurement, the technology is to determine whether to modify a synchronization barrier policy to include a synchronization barrier to impede synchronization of one or more synchronizing parameters of one of the layers during a second window of the training. The technology is further to impede the synchronization of the one or more synchronizing parameters of the one of the layers during the second window if the synchronization barrier policy is modified to include the synchronization barrier.