公开(公告)号：US11742407B2

公开(公告)日：2023-08-29

申请号：US16700757

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Sou-Chi Chang ,  Devin Merrill ,  I-Cheng Tung ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Ian A. Young ,  Matthew V. Metz ,  Uygar E. Avci ,  Chia-Ching Lin ,  Owen Loh ,  Shriram Shivaraman ,  Eric Charles Mattson

IPC: H01L29/51 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/512 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7851

Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

公开(公告)号：US20220199619A1

公开(公告)日：2022-06-23

申请号：US17133208

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Tristan Tronic ,  Shriram Shivaraman ,  Devin Merrill ,  Tobias Brown-Heft ,  Kirby Maxey ,  Matthew Metz ,  Ian Young

IPC: H01L27/092 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02 ,  H01L43/08 ,  H01L45/00 ,  H01L43/12

Abstract: A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes Hf1-xZxO2, where 0.33

公开(公告)号：US11616130B2

公开(公告)日：2023-03-28

申请号：US16363632

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Uygar Avci ,  Devin Merrill ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Owen Loh

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.

公开(公告)号：US11973143B2

公开(公告)日：2024-04-30

申请号：US16368088

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Benjamin Chu-Kung ,  Subrina Rafique ,  Devin Merrill ,  Ashish Agrawal ,  Harold Kennel ,  Yang Cao ,  Dipanjan Basu ,  Jessica Torres ,  Anand Murthy

IPC: H01L21/84 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US20200312976A1

公开(公告)日：2020-10-01

申请号：US16363632

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Uygar Avci ,  Devin Merrill ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Owen Loh

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.