公开(公告)号：US11073554B2

公开(公告)日：2021-07-27

申请号：US16586731

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Asad Azam ,  Dhinesh A/L Sasidaran ,  R Selvakumar Raja Gopal

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  G06F11/10

Abstract: Apparatuses of a scan controller include memory and circuitry, where the circuitry is configured to respond to a first signal by sending a second signal to isolate state retention elements from non-state retention elements in a scan chain of power gating circuitry and cycling through the scan chain while obtaining state retention data from the state retention elements during each cycle. The circuitry may be further configured to determine a first error detection code from the state retention data and store the error detection code in the memory. The circuitry may be configured to determine a second error detection code in response to another signal and compare the first error detection code with the second error detection code. The circuitry may be configured to send a signal indicating that the state retention data is corrupted if the first error detection code does not match the second error detection code.