公开(公告)号：US20250113580A1

公开(公告)日：2025-04-03

申请号：US18374528

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Leonard Guler ,  Shaun Mills ,  Joseph D'Silva ,  Ehren Mannebach ,  Mauro Kobrinsky ,  Charles H. Wallace ,  Kalpesh Mahajan ,  Vivek Vishwakarma ,  Dincer Unluer ,  Jessica Panella

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Devices, transistor structures, systems, and techniques are described herein related to contacting source and drain transistor structures from the device backside at small dimensions and cell sizes. A first subset of dummy contact structures are removed and backfilled with contact metal and a first etch stop material. A second subset of dummy contact structures are removed and backfilled with contact metal and a second etch stop material. Subsequent metallization contacts to the first and second contacts are made using two masking/selective etch processes such that any misalignment to the other contact type does not allow contact due to the pertinent etch stop material.

公开(公告)号：US20230395697A1

公开(公告)日：2023-12-07

申请号：US17831800

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Munzarin F. Qayyum ,  Marko Radosavljevic ,  Cheng-Ying Huang ,  Willy Rachmady ,  Rohit Galatage ,  Jami A. Wiedemer ,  David Bennett ,  Dincer Unluer ,  Venkata Aditya Addepalli

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0669 ,  H01L21/823807

Abstract: A semiconductor structure includes a second device stacked over a first device. In an example, the first device includes (i) a first source region, (ii) a first drain region, (iii) a body including a semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. The body can be, for instance, a nanoribbon, nanosheet, or nanowire. In an example, the second device comprises (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the second device lacks a continuous body extending laterally from the second source region to the second drain region.

公开(公告)号：US20250132245A1

公开(公告)日：2025-04-24

申请号：US18491111

申请日：2023-10-20

Applicant: Intel Corporation

Inventor： Tofizur RAHMAN ,  Conor P. Puls ,  Payam Amin ,  Santhosh Koduri ,  Clay Mortensen ,  Bozidar Marinkovic ,  Shivani Falgun Patel ,  Richard Bonsu ,  Jaladhi Mehta ,  Dincer Unluer

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more self-insulated vias is described herein. In one example, an IC structure includes a via surrounded by an insulator material and a layer of insulator material between a conductive material of the via and the surrounding insulator material. In one example, the layer of insulator material has one or more material properties that are different than the surrounding insulator material, including one or more of a different density, a different dielectric constant, and a different material composition.