公开(公告)号：US20220414011A1

公开(公告)日：2022-12-29

申请号：US17355856

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Saikat Mandal ,  Eric Hoekstra ,  Vasanth Ranganathan ,  Prasoonkumar Surti

IPC: G06F12/0855 ,  G06F12/0815 ,  G06T7/50

Abstract: Methods, systems and apparatuses provide for graphics processor technology that determines whether a first cache line allocated for early depth testing overlaps a second cache line allocated for late depth testing, and when the first cache line overlaps the second cache line, switches the first cache line to be allocated for late depth testing, and bypasses an early depth test for the first cache line. The technology can also compare coordinates of the first cache line with the coordinates of the second cache line, where an overlap is determined when coordinates for at least one pixel in the first cache line match coordinates for at least one pixel in the second cache line. Additionally, the technology can also perform early depth testing on each pixel in the first cache line when the first cache line does not overlap any existing cache lines allocated for late depth testing.

公开(公告)号：US12100103B2

公开(公告)日：2024-09-24

申请号：US17390198

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Eric Hoekstra ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Subramaniam Maiyuran ,  Kalyan Bhiravabhatla

IPC: G06T17/10 ,  G06T1/20 ,  G06T15/00 ,  G06T19/20

CPC classification number: G06T17/10 ,  G06T1/20 ,  G06T19/20 ,  G06T15/005 ,  G06T2219/2004

Abstract: Methods, systems and apparatuses provide for graphics processor technology that generates attribute plane coefficients based on barycentric coefficients, wherein the attribute plane coefficients are generated on a per polygon basis, and interpolates one or more pixel attributes based on the attribute plane coefficients. In one example, the technology excludes the barycentric coefficients from one or more per pixel operations.

公开(公告)号：US12182023B2

公开(公告)日：2024-12-31

申请号：US17355856

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Saikat Mandal ,  Eric Hoekstra ,  Vasanth Ranganathan ,  Prasoonkumar Surti

IPC: G06F12/0855 ,  G06F12/0815 ,  G06T7/50

Abstract: Methods, systems and apparatuses provide for graphics processor technology that determines whether a first cache line allocated for early depth testing overlaps a second cache line allocated for late depth testing, and when the first cache line overlaps the second cache line, switches the first cache line to be allocated for late depth testing, and bypasses an early depth test for the first cache line. The technology can also compare coordinates of the first cache line with the coordinates of the second cache line, where an overlap is determined when coordinates for at least one pixel in the first cache line match coordinates for at least one pixel in the second cache line. Additionally, the technology can also perform early depth testing on each pixel in the first cache line when the first cache line does not overlap any existing cache lines allocated for late depth testing.

公开(公告)号：US20230064069A1

公开(公告)日：2023-03-02

申请号：US17390198

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Eric Hoekstra ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Subramaniam Maiyuran ,  Kalyan Bhiravabhatla

IPC: G06T17/10 ,  G06T19/20 ,  G06T1/20

Abstract: Methods, systems and apparatuses provide for graphics processor technology that generates attribute plane coefficients based on barycentric coefficients, wherein the attribute plane coefficients are generated on a per polygon basis, and interpolates one or more pixel attributes based on the attribute plane coefficients. In one example, the technology excludes the barycentric coefficients from one or more per pixel operations.

公开(公告)号：US20220414816A1

公开(公告)日：2022-12-29

申请号：US17357431

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Eric Hoekstra

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60 ,  G06T15/50

Abstract: Methods, systems and apparatuses may provide for technology that identifies that a first thread group of a pixel location is associated with a first shading rate, identifies that a second thread group of the pixel location is associated with a second shading rate, wherein the first shading rate is different from the second shading rate. The technology marks a dependency of the first thread group on the second thread group.