公开(公告)号：US09660799B1

公开(公告)日：2017-05-23

申请号：US14950319

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Ernest Knoll ,  Ofer Nathan ,  Michael Mishaeli ,  Krishnakanth V. Sistla ,  Ariel Sabba ,  Shani Rehana ,  Ariel Szapiro ,  Tsvika Kurts ,  Ofer Levy

IPC: G06F1/06 ,  H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0331 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  H04L7/0025 ,  H04L7/005 ,  Y02D10/126

Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

公开(公告)号：US20220091168A1

公开(公告)日：2022-03-24

申请号：US17543956

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Yossi Ben Simon ,  Ido Kahan ,  Ofir Shwartz ,  Ernest Knoll ,  Assaf Admoni

IPC: G01R23/02 ,  G06F1/12

Abstract: An apparatus comprising a frequency monitor circuitry to receive a first clock signal, a second clock signal and an expected frequency ratio, determine whether a ratio between the first clock signal and the second clock signal matches an expected an expected frequency ratio and generate an error signal upon a determination that the ratio between the first clock signal and the second clock signal does not match the expected frequency ratio.

公开(公告)号：US20210036708A1

公开(公告)日：2021-02-04

申请号：US16528435

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Ariel Gur ,  Daniel J. Ragland ,  Yoav Ben-Raphael ,  Ernest Knoll

IPC: H03L7/18 ,  H03L7/187 ,  H03L7/14

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.

公开(公告)号：US20170149554A1

公开(公告)日：2017-05-25

申请号：US14950319

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Ernest Knoll ,  Ofer Nathan ,  Michael Mishaeli ,  Krishnakanth V. Sistla ,  Ariel Sabba ,  Shani Rehana ,  Ariel Szapiro ,  Tsvika Kurts ,  Ofer Levy

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0331 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  H04L7/0025 ,  H04L7/005 ,  Y02D10/126

Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

公开(公告)号：US12050483B2

公开(公告)日：2024-07-30

申请号：US17021900

申请日：2020-09-15

Applicant: Intel Corporation

Inventor： Yossi Ben Simon ,  Ariel Avital ,  Arkady Vaisman ,  Ernest Knoll

IPC: G06F1/04 ,  G06F1/10 ,  H03K19/173 ,  H03K19/20

CPC classification number: G06F1/10 ,  H03K19/1737 ,  H03K19/20

Abstract: Techniques and mechanisms for determining an amount of skew between two clock signals. In an embodiment, detector circuitry receives a first signal and a signal which indicate (respectively) a NAND combination of clock signals, and a NOR combination of the clock signals. The detector circuitry evaluates a first length of time that the first signal indicates a respective first logic state, and a second length of time that the second signal indicates a respective second logic state. The skew is calculated based on a difference between the first length of time and the second length of time. In another embodiment, one of the first signal or the second signal is generated with a combinatorial logic gate, a transistor of which is relatively large, as compared to another transistor which is to operate based on one of the first signal, the second signal, or the clock signals.

公开(公告)号：US20220083093A1

公开(公告)日：2022-03-17

申请号：US17021900

申请日：2020-09-15

Applicant: Intel Corporation

Inventor： Yossi Ben Simon ,  Ariel Avital ,  Arkady Vaisman ,  Ernest Knoll

IPC: G06F1/10 ,  H03K19/20 ,  H03K19/173

Abstract: Techniques and mechanisms for determining an amount of skew between two clock signals. In an embodiment, detector circuitry receives a first signal and a signal which indicate (respectively) a NAND combination of clock signals, and a NOR combination of the clock signals. The detector circuitry evaluates a first length of time that the first signal indicates a respective first logic state, and a second length of time that the second signal indicates a respective second logic state. The skew is calculated based on a difference between the first length of time and the second length of time. In another embodiment, one of the first signal or the second signal is generated with a combinatorial logic gate, a transistor of which is relatively large, as compared to another transistor which is to operate based on one of the first signal, the second signal, or the clock signals.

公开(公告)号：US10958278B2

公开(公告)日：2021-03-23

申请号：US16528435

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Ariel Gur ,  Daniel J. Ragland ,  Yoav Ben-Raphael ,  Ernest Knoll

IPC: H03D3/24 ,  H03L7/18 ,  H03L7/14 ,  H03L7/187

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.