公开(公告)号：US20230409493A1

公开(公告)日：2023-12-21

申请号：US17836468

申请日：2022-06-09

Applicant: Intel Corporation

Inventor： Rupin Vakharwala ,  Garrett Drown

IPC: G06F12/14 ,  G06F12/02

CPC classification number: G06F12/1491 ,  G06F12/1433 ,  G06F2212/7201 ,  G06F12/0292 ,  G06F12/0246

Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to optimizing memory access and minimizing performance degradation due to faulty or malicious devices attempting to access improper memory locations. Faulty/malicious devices' memory accesses are quickly blocked reducing performance degradation due to the avoidance of costly memory lookups and fault generation/processing. Other embodiments may be described and/or claimed.

公开(公告)号：US20170286118A1

公开(公告)日：2017-10-05

申请号：US15088327

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： James A. Coleman ,  Philip C. Arellano ,  Garrett Drown

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/08

Abstract: A processor of an aspect includes a plurality of caches at a plurality of different cache levels. The processor also includes a decode unit to decode a fetch instruction. The fetch instruction is to indicate address information for a memory location, and the fetch instruction is to indicate a cache level of the plurality of different cache levels. The processor also includes a cache controller coupled with the decode unit, and coupled with a cache at the indicated cache level. The cache controller, in response to the fetch instruction, is to store data associated with the memory location in the cache, wherein the fetch instruction is architecturally guaranteed to be completed. Other processors, methods, systems, and machine-readable storage mediums storing instructions are disclosed.