公开(公告)号：US11232056B2

公开(公告)日：2022-01-25

申请号：US16464560

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Wenqian Yu ,  Cunming Liang ,  Ping Yu ,  Shun Hao ,  Helin Zhang

IPC: G06F13/38 ,  G06F9/30 ,  G06F9/355 ,  G06F9/46

Abstract: There is disclosed in an example, an endpoint apparatus for an interconnect, comprising: a mechanical and electrical interface to the interconnect; and one or more logic elements comprising an interface vector engine to: receive a first scalar transaction for the interface; determine that the first scalar transaction meets a criterion for vectorization; receive a second scalar transaction for the interface; determine that the second transaction meets the criterion for vectorization; vectorize the first scalar transaction and second scalar transaction into a vector transaction; and send the vector transaction via the electrical interface.

公开(公告)号：US20200301861A1

公开(公告)日：2020-09-24

申请号：US16464560

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Wenqian Yu ,  Cunming Liang ,  Ping Yu ,  Shun Hao ,  Helin Zhang

IPC: G06F13/38 ,  G06F9/46 ,  G06F9/30 ,  G06F9/355

Abstract: There is disclosed in an example, an endpoint apparatus for an interconnect, comprising: a mechanical and electrical interface to the interconnect; and one or more logic elements comprising an interface vector engine to: receive a first scalar transaction for the interface; determine that the first scalar transaction meets a criterion for vectorization; receive a second scalar transaction for the interface; determine that the second transaction meets the criterion for vectorization; vectorize the first scalar transaction and second scalar transaction into a vector transaction; and send the vector transaction via the electrical interface