公开(公告)号：US11416248B2

公开(公告)日：2022-08-16

申请号：US16833597

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Jaewoong Sim ,  Alaa Alameldeen ,  Eriko Nurvitadhi ,  Deborah Marr

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/485 ,  G06F7/556

Abstract: An apparatus and method for compressing floating-point values. For example, one embodiment of a processor comprises: instruction fetch circuitry to fetch instructions from a memory, the instructions including floating-point instructions; execution circuitry to execute the floating-point instructions, each floating-point instruction having one or more floating-point operands, each floating-point operand comprising an exponent value and a significand value; floating-point compression circuitry to compress a plurality of the exponent values associated with a corresponding plurality of the floating-point operands, the floating-point compression circuitry comprising: base generation circuitry to evaluate the plurality of the exponent values to generate a first base value; and delta generation circuitry to determine a difference between the plurality of exponent values and the first base value and to generate a corresponding first plurality of delta values, wherein the floating-point compression circuitry is to store the first base value and the corresponding first plurality of delta values as a plurality of compressed exponent values.

公开(公告)号：US11093250B2

公开(公告)日：2021-08-17

申请号：US16147694

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Jonathan Pearce ,  David Sheffield ,  Srikanth Srinivasan ,  Jaewoong Sim ,  Andrey Ayupov

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/50

Abstract: An apparatus and method for efficiently processing invariant operations on a parallel execution engine. For example, one embodiment of a processor comprises: a plurality of parallel execution lanes comprising execution circuitry and registers to concurrently execute a plurality of threads; front end circuitry coupled to the plurality of parallel execution lanes, the front end circuitry to arrange the threads into parallel execution groups and schedule operations of the threads to be executed across the parallel execution lanes, wherein the front end circuitry is to dynamically evaluate one or more variables associated with the operations to determine if one or more conditionally invariant operations will be invariant across threads of a parallel execution group and/or across the parallel execution lanes; a scheduler of the front end circuitry to responsively schedule a shared thread upon a determination that a conditionally invariant operation will be invariant across threads of a parallel execution group and/or across the parallel execution lanes.

公开(公告)号：US09921972B2

公开(公告)日：2018-03-20

申请号：US15281383

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Christopher B. Wilkerson ,  Alaa R. Alameldeen ,  Zeshan A. Chishti ,  Jaewoong Sim

IPC: G06F12/00 ,  G06F12/122 ,  G11C7/10 ,  G06F3/06 ,  G06F12/0893

CPC classification number: G06F12/122 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0673 ,  G06F12/0893 ,  G06F2212/1016 ,  G11C7/1072

Abstract: An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.

公开(公告)号：US09472248B2

公开(公告)日：2016-10-18

申请号：US14228856

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Christopher B. Wilkerson ,  Alaa R. Alameldeen ,  Zeshan A. Chishti ,  Jaewoong Sim

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F12/122 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0673 ,  G06F12/0893 ,  G06F2212/1016 ,  G11C7/1072

Abstract: An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.

Abstract translation: 描述了用于实现异构存储器子系统的装置和方法。 例如，处理器的一个实施例包括：存储器映射逻辑，用于将系统存储器空间细分成多个存储器块，并且跨越第一存储器和第二存储器映射存储器块，第一存储器具有第一组存储器访问 特性和第二存储器具有不同于第一组存储器访问特性的第二组存储器存取特性; 以及动态重映射逻辑，用于至少部分地基于访问存储器块的检测频率来交换第一和第二存储器之间的存储器块。