公开(公告)号：US10923443B2

公开(公告)日：2021-02-16

申请号：US16369708

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D Ecton

IPC: H01L23/495 ,  H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US20230077633A1

公开(公告)日：2023-03-16

申请号：US17476080

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Pooya Tadayon ,  John Heck ,  Eric J. Moret ,  Tarek A. Ibrahim ,  Zhichao Zhang ,  Jeremy D Ecton

IPC: G02B6/42

Abstract: An electronic device comprises a photonic integrated circuit (PIC) including at least one waveguide, an emitting lens disposed on the PIC to emit light from the at least one waveguide in a direction substantially parallel to a first surface of the PIC, and an optical element disposed on the PIC and having a reflective surface configured to direct light emitted from the emitting lens in a direction away from the first surface of the PIC.

公开(公告)号：US11652071B2

公开(公告)日：2023-05-16

申请号：US17158634

申请日：2021-01-26

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D Ecton

IPC: H01L23/495 ,  H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

CPC classification number: H01L23/642 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L28/40

Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US20210151393A1

公开(公告)日：2021-05-20

申请号：US17158634

申请日：2021-01-26

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D Ecton

IPC: H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US10910327B2

公开(公告)日：2021-02-02

申请号：US16369681

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Yonggang Li ,  Brandon C Marin ,  Vahidreza Parichehreh ,  Jeremy D Ecton

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.