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公开(公告)号：US20230318211A1
公开(公告)日：2023-10-05
申请号：US18130404
申请日：2023-04-03
Applicant: Intel Corporation
CPC classification number: H01R12/721 , H01R13/5219 , H01R13/5216 , H01R4/023 , H05K7/20236
Abstract: Methods and apparatus relating to liquid-proof edge connector solutions for immersion cooling are described. In one embodiment, a seal prevents a cooling liquid to cause electrical contact with a pin of an edge card to be inserted in a connector. And, an adhesive prevents the cooling liquid to cause electrical contact with a terminal of the connector. Other embodiments are also claimed and disclosed.
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公开(公告)号：US11276911B2
公开(公告)日：2022-03-15
申请号：US16164352
申请日：2018-10-18
Applicant: Intel Corporation
Inventor： Jingbo Li , Kai Xiao , Howard Heck , Kai Wang
Abstract: In accordance with embodiments disclosed herein, there is provided a high-density low-loss cable and connector assembly. A cable assembly includes a first cable connector, a bulk cable section, and a first cable transition section. The bulk cable section includes a first plurality of conductive wires of a first wire thickness. The first cable transition section includes a second plurality of conductive wires that has a first distal end connected to the bulk cable section and a second distal end connected to the first cable connector. Each of the second plurality of conductive wires transitions from the first wire thickness at the first distal end to a second wire thickness that is less than the first wire thickness at the second distal end. Each of the second plurality of conductive wires in the first distal end is connected to a corresponding conductive wire of the first plurality of conductive wires.
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公开(公告)号：US10922114B2
公开(公告)日：2021-02-16
申请号：US15735578
申请日：2016-12-12
Applicant: Intel Corporation
Inventor： Bing Zhu , Kai Wang , Peng Zou , Fangjian Zhong
Abstract: A processing system includes a first register to store an invalidation mode flag associated with a virtual processor identifier (VPID) and a processing core, communicatively coupled to the first register, the processing core comprising a logic circuit to execute a virtual machine monitor (VMM) environment, the VMM environment comprising a root mode VMM supporting a non-root mode VMM, the non-root mode VMM to execute a virtual machine (VM) identified by the VPID, the logic circuit further comprising an invalidation circuit to execute a virtual processor invalidation (INVVPID) instruction issued by the non-root mode VMM, the INVVPID instruction comprising a reference to an INVVPID descriptor that specifies a linear address and the VPID and responsive to determining that the invalidation mode flag is set, invalidate, without triggering a VM exit event, a memory address mapping associated with the linear address.
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公开(公告)号：US20200249983A1
公开(公告)日：2020-08-06
申请号：US16648751
申请日：2017-12-27
Applicant: INTEL CORPORATION
Inventor： Kai Wang , Bing Zhu , Fangjian Zhong , Yadong Qi , Peng Zou
Abstract: The systems and methods for enabling a lightweight VMM to efficiently interrupt virtual machines are provided. In some examples, the lightweight VMM is configured to utilize a self IPI to deliver external interrupts to the virtual machines. The self IPI may be generated by writing one or more values, including an identifier of the external interrupt, to an ICR of a programmable interrupt controller. The programmable interrupt controller may retrieve the one or more values from the ICR, identify the external interrupt and process the external interrupt, which culminates in the external interrupt being written to an IDT of a virtual machine targeted for interrupt delivery by the lightweight VMM.
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公开(公告)号：US10963281B2
公开(公告)日：2021-03-30
申请号：US16148245
申请日：2018-10-01
Applicant: Intel Corporation
Inventor： Kai Wang , Bing Zhu , Peng Zou , Manohar Castelino
Abstract: Memory security technologies are described. An example processing device includes a processor core and a memory controller coupled to the processor core and a memory. The processor core can determine that an exit condition to transfer control of a resource for a processor core from a first virtual machine monitor (VMM) to a second VMM has occurred. The processor core can also determine whether a control virtual machine control structure (VMCS) link pointer is valid. The processor core can also determine whether a reason value corresponding to the control VMCS link pointer is set. The processor core can also determine whether the reason value is set to zero. The processor core can also determining whether an exception bit corresponding to a specific exception type of a reason value is set. The processor core can also transfer a control of the resource from the first VMM to the second VMM.
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Patent Agency Ranking
公开(公告)号：US10146570B2
公开(公告)日：2018-12-04
申请号：US15118844
申请日：2015-09-25
Applicant: INTEL CORPORATION , Kai Wang , Bing Zhu , Peng Zou , Manohar Castelino
Inventor： Kai Wang , Bing Zhu , Peng Zou , Manohar Castelino
Abstract: Memory security technologies are described. An example processing device includes a processor core and a memory controller coupled to the processor core and a memory. The processor core can determine that an exit condition to transfer control of a resource for a processor core from a first virtual machine monitor (VMM) to a second VMM has occurred. The processor core can also determine whether a control virtual machine control structure (VMCS) link pointer is valid. The processor core can also determine whether a reason value corresponding to the control VMCS link pointer is set. The processor core can also determine whether the reason value is set to zero. The processor core can also determining whether an exception bit corresponding to a specific exception type of a reason value is set. The processor core can also transfer a control of the resource from the first VMM to the second VMM.
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7.发明授权Processors, methods, and systems to enforce blacklisted paging structure indication values 有权处理器，方法和系统来执行黑名单的寻呼结构指示值公开(公告)号：US09223602B2
公开(公告)日：2015-12-29
申请号：US13730798
申请日：2012-12-28
Applicant: Intel Corporation
Inventor： Bing Zhu , Luhai Chen , Peng Zou , Kai Wang
CPC classification number: G06F9/45558 , G06F9/3004 , G06F9/30076 , G06F9/45533 , G06F2009/45583
Abstract: A method of an aspect includes receiving an indication of an attempt by a virtual machine to modify a paging structure identification storage location to have a given value. It is determined that the given value matches at least one of a set of one or more blacklist values. The attempt by the virtual machine to modify the paging structure identification storage location to have the given value is trapped to a virtual machine monitor. Other methods, apparatus, and systems are also disclosed.
Abstract translation: 一种方面的方法包括：接收虚拟机尝试的指示，以修改寻呼结构标识存储位置以具有给定值。 确定给定值与一个或多个黑名单值的集合中的至少一个匹配。 虚拟机尝试将分页结构标识存储位置修改为具有给定值被捕获到虚拟机监视器。 还公开了其它方法，装置和系统。
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8.发明授权公开(公告)号：US10360055B2
公开(公告)日：2019-07-23
申请号：US14947416
申请日：2015-11-20
Applicant: Intel Corporation
Inventor： Bing Zhu , Luhai Chen , Peng Zou , Kai Wang
Abstract: A method of an aspect includes receiving an indication of an attempt by a virtual machine to modify a paging structure identification storage location to have a given value. It is determined that the given value matches at least one of a set of one or more blacklist values. The attempt by the virtual machine to modify the paging structure identification storage location to have the given value is trapped to a virtual machine monitor. Other methods, apparatus, and systems are also disclosed.
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公开(公告)号：US10884784B2
公开(公告)日：2021-01-05
申请号：US16648751
申请日：2017-12-27
Applicant: INTEL CORPORATION
Inventor： Kai Wang , Bing Zhu , Fangjian Zhong , Yadong Qi , Peng Zou
Abstract: The systems and methods for enabling a lightweight VMM to efficiently interrupt virtual machines are provided. In some examples, the lightweight VMM is configured to utilize a self IPI to deliver external interrupts to the virtual machines. The self IPI may be generated by writing one or more values, including an identifier of the external interrupt, to an ICR of a programmable interrupt controller. The programmable interrupt controller may retrieve the one or more values from the ICR, identify the external interrupt and process the external interrupt, which culminates in the external interrupt being written to an IDT of a virtual machine targeted for interrupt delivery by the lightweight VMM.
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10.发明申请PROCESSORS, METHODS, AND SYSTEMS TO ENFORCE BLACKLISTED PAGING STRUCTURE INDICATION VALUES 审中-公开处理器，方法和系统，以执行黑名单结构指示值公开(公告)号：US20160077864A1
公开(公告)日：2016-03-17
申请号：US14947416
申请日：2015-11-20
Applicant: INTEL CORPORATION
Inventor： Bing Zhu , Luhai Chen , Peng Zou , Kai Wang
IPC: G06F9/455
CPC classification number: G06F9/45558 , G06F9/3004 , G06F9/30076 , G06F9/45533 , G06F2009/45583
Abstract: A method of an aspect includes receiving an indication of an attempt by a virtual machine to modify a paging structure identification storage location to have a given value. It is determined that the given value matches at least one of a set of one or more blacklist values. The attempt by the virtual machine to modify the paging structure identification storage location to have the given value is trapped to a virtual machine monitor. Other methods, apparatus, and systems are also disclosed.
Abstract translation: 一种方面的方法包括：接收虚拟机尝试的指示，以修改寻呼结构标识存储位置以具有给定值。 确定给定值与一个或多个黑名单值的集合中的至少一个匹配。 虚拟机尝试将分页结构标识存储位置修改为具有给定值被捕获到虚拟机监视器。 还公开了其它方法，装置和系统。
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