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    PROCESSORS, METHODS, AND SYSTEMS FOR A CONFIGURABLE SPATIAL ACCELERATOR WITH SECURITY, POWER REDUCTION, AND PERFORMACE FEATURES
    3.
    发明申请
    PROCESSORS, METHODS, AND SYSTEMS FOR A CONFIGURABLE SPATIAL ACCELERATOR WITH SECURITY, POWER REDUCTION, AND PERFORMACE FEATURES 审中-公开

    公开(公告)号：US20190004878A1

    公开(公告)日：2019-01-03

    申请号：US15640542

    申请日：2017-07-01

    Applicant: Intel Corporation

    Inventor： Michael C. Adler ,  Kermin Fleming ,  Kent D. Glossop ,  Simon C. Steely, JR.

    IPC: G06F9/54 ,  G06F9/30 ,  G06F21/62 ,  G06F13/16

    Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of two dataflow graphs each comprising a plurality of nodes, wherein a first dataflow graph and a second dataflow graph are be overlaid into a first and second portion, respectively, of the interconnect network and a first and second subset, respectively, of the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the first and second subsets of the plurality of processing elements are to perform a first and second operation, respectively, when incoming first and second, respectively, operand sets arrive at the plurality of processing elements.

    Processors, methods, and systems with a configurable spatial accelerator
    5.
    发明授权
    Processors, methods, and systems with a configurable spatial accelerator 有权

    公开(公告)号：US10416999B2

    公开(公告)日：2019-09-17

    申请号：US15396395

    申请日：2016-12-30

    Applicant: Intel Corporation

    Inventor： Kermin Fleming ,  Kent D. Glossop ,  Simon C. Steely, Jr.

    IPC: G06F9/30 ,  G06F15/82 ,  G06F13/42

    Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a second operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements.

    PROCESSORS, METHODS, AND SYSTEMS FOR DEBUGGING A CONFIGURABLE SPATIAL ACCELERATOR
    6.
    发明申请
    PROCESSORS, METHODS, AND SYSTEMS FOR DEBUGGING A CONFIGURABLE SPATIAL ACCELERATOR 审中-公开

    公开(公告)号：US20190095383A1

    公开(公告)日：2019-03-28

    申请号：US15719281

    申请日：2017-09-28

    Applicant: Intel Corporation

    Inventor： Kermin Fleming ,  Simon C. Steely, JR. ,  Kent D. Glossop

    IPC: G06F15/80

    Abstract: Systems, methods, and apparatuses relating to debugging a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. At least a first of the plurality of processing elements is to enter a halted state in response to being represented as a first of the plurality of dataflow operators.

    Processors, methods, and systems for debugging a configurable spatial accelerator
    7.
    发明授权
    Processors, methods, and systems for debugging a configurable spatial accelerator 有权

    公开(公告)号：US11086816B2

    公开(公告)日：2021-08-10

    申请号：US15719281

    申请日：2017-09-28

    Applicant: Intel Corporation

    Inventor： Kermin Fleming ,  Simon C. Steely, Jr. ,  Kent D. Glossop

    IPC: G06F15/80

    Abstract: Systems, methods, and apparatuses relating to debugging a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. At least a first of the plurality of processing elements is to enter a halted state in response to being represented as a first of the plurality of dataflow operators.

    Processors, methods, and systems with a configurable spatial accelerator
    8.
    发明授权
    Processors, methods, and systems with a configurable spatial accelerator 有权

    公开(公告)号：US10515046B2

    公开(公告)日：2019-12-24

    申请号：US15640543

    申请日：2017-07-01

    Applicant: Intel Corporation

    Inventor： Kermin Fleming ,  Kent D. Glossop ,  Simon C. Steely, Jr.

    IPC: G06F13/42 ,  G06F9/50 ,  G06F15/82

    Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a synchronizer circuit coupled between an interconnect network of a first tile and an interconnect network of a second tile and comprising storage to store data to be sent between the interconnect network of the first tile and the interconnect network of the second tile, the synchronizer circuit to convert the data from the storage between a first voltage or a first frequency of the first tile and a second voltage or a second frequency of the second tile to generate converted data, and send the converted data between the interconnect network of the first tile and the interconnect network of the second tile

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