公开(公告)号：US20240222461A1

公开(公告)日：2024-07-04

申请号：US18091201

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Ande Kitamura ,  Carl H. Naylor ,  Kevin O'Brien ,  Kirby Maxey ,  Chelsey Dorow ,  Ashish Verma Penumatcha ,  Scott B. Clendenning ,  Uygar Avci ,  Matthew Metz ,  Chia-Ching Lin ,  Sudarat Lee ,  Mahmut Sami Kavrik ,  Carly Rogan ,  Paul Gutwin

IPC: H01L29/45 ,  H01L21/02 ,  H01L21/443 ,  H01L23/528 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/775

CPC classification number: H01L29/45 ,  H01L21/02568 ,  H01L21/443 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/7606 ,  H01L29/775

Abstract: A transistor in an integrated circuit (IC) die includes source and drain terminals having a bulk material enclosed by a liner material. A nanoribbon channel region couples the source and drain terminals. The nanoribbon may include a transition metal and a chalcogen. The liner material may contact ends and upper and lower surfaces of the nanoribbon. The transistor may be in an interconnect layer. The source and drain terminals may be formed by conformally depositing the liner material over the ends of the nanoribbon and in voids opened in the IC die.

公开(公告)号：US20240222126A1

公开(公告)日：2024-07-04

申请号：US18147644

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Uygar Avci ,  Brandon Holybee ,  Jennifer Lux ,  Kevin O'Brien ,  Shida Tan

IPC: H01L21/266 ,  H01L21/265

CPC classification number: H01L21/266 ,  H01L21/26506

Abstract: This disclosure describes systems, apparatus, methods, and devices related to fabrication using ion beams. The device may apply an ion beam targeted to at least one of one or more regions of a top layer, a metal layer placed on top of the top layer, or one or more ion stoppers placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify the material characteristics of the 2D material at the one or more regions of the top layer. The device may create a bond between the one or more 2D and metal layers to the one or more regions of the top layer where the material characteristics of the 2D material have been modified due to the impinging ion beam.

公开(公告)号：US20240222073A1

公开(公告)日：2024-07-04

申请号：US18147636

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Shida Tan ,  Uygar Avci ,  Brandon Holybee ,  Kirby Maxey ,  Kevin O'Brien ,  Mahmut Sami Kavrik

IPC: H01J37/317 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01J37/3174 ,  H01L21/0279 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32139 ,  H01J2237/3174 ,  H01J2237/31755

Abstract: This disclosure describes systems, apparatus, methods, and devices related to ion beams fabrication. A device may overlay a wafer assembly of one or more layers with a top layer comprised of a material having 2D material characteristics. The device may be fabricated by applying an ion beam targeted to at least one of one or more regions of the top layer or a resist layer placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify material characteristics of the resist layer or to perform milling of the top layer or other layers of the one or more layers of the wafer assembly.

公开(公告)号：US11854894B2

公开(公告)日：2023-12-26

申请号：US17112697

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Valluri R. Rao ,  Patrick Morrow ,  Rishabh Mehandru ,  Doug Ingerly ,  Kimin Jun ,  Kevin O'Brien ,  Paul Fischer ,  Szuya S. Liao ,  Bruce Block

IPC: H01L21/822 ,  H01L21/306 ,  H01L21/683 ,  H01L21/8238 ,  H01L21/66 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  G01R1/073 ,  H01L25/065

CPC classification number: H01L21/8221 ,  H01L21/30625 ,  H01L21/6835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L22/14 ,  H01L23/528 ,  H01L23/53233 ,  H01L24/03 ,  H01L24/05 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/20 ,  G01R1/07307 ,  H01L24/08 ,  H01L25/0657 ,  H01L27/1214 ,  H01L27/1222 ,  H01L29/66545 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/08147 ,  H01L2225/06565

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

公开(公告)号：US11683939B2

公开(公告)日：2023-06-20

申请号：US16396451

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Benjamin Buford ,  Angeline Smith ,  Noriyuki Sato ,  Tanay Gosavi ,  Kaan Oguz ,  Christopher Wiegand ,  Kevin O'Brien ,  Tofizur Rahman ,  Gary Allen ,  Sasikanth Manipatruni ,  Emily Walker

IPC: H10B61/00 ,  H10N50/10 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10B61/22 ,  H10N50/10 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80

Abstract: A memory apparatus includes a first electrode having a spin orbit material. The memory apparatus further includes a first memory device on a portion of the first electrode and a first dielectric adjacent to a sidewall of the first memory device. The memory apparatus further includes a second memory device on a portion of the first electrode and a second dielectric adjacent to a sidewall of the second memory device. A second electrode is on and in contact with a portion of the first electrode, where the second electrode is between the first memory device and the second memory device. The second electrode has a lower electrical resistance than an electrical resistance of the first electrode. The memory apparatus further includes a first interconnect structure and a second interconnect, each coupled with the first electrode.

公开(公告)号：US11444237B2

公开(公告)日：2022-09-13

申请号：US16024393

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Gary Allen ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young ,  Ben Buford

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32 ,  H01L43/10 ,  G11C11/14

Abstract: A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.

公开(公告)号：US11430943B2

公开(公告)日：2022-08-30

申请号：US16022561

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Kaan Oguz ,  Noriyuki Sato ,  Charles Kuo ,  Mark Doczy

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/12 ,  H01F41/30 ,  H01L27/22 ,  H01L43/10

Abstract: A magnetic tunneling junction (MTJ) memory device including a free and fixed (reference) magnet between first and second electrodes, and a synthetic antiferromagnet structure (SAF) structure between the fixed magnet and one of the electrodes. The SAF structure includes a magnetic skyrmion. Two magnetic skyrmions within a SAF structure may have opposing polarity. A SAF structure may further include a coupling layer between two magnetic layers, as well as interface layers separated from the coupling layer by one of the magnetic layers. The coupling layer may have a spin-orbit coupling effect on the magnetic layers that is of a sign opposite that of the interface layers, for example to promote formation of the magnetic skyrmions.

公开(公告)号：US11417830B2

公开(公告)日：2022-08-16

申请号：US16024709

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Gary Allen ,  Kaan Oguz ,  Kevin O'Brien ,  Noriyuki Sato ,  Ian Young ,  Dmitri Nikonov

IPC: H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12 ,  H01L43/10

Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.

公开(公告)号：US11374164B2

公开(公告)日：2022-06-28

申请号：US16024714

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Kaan Oguz ,  Christopher Wiegand ,  Angeline Smith ,  Noriyuki Sato ,  Kevin O'Brien ,  Benjamin Buford ,  Ian Young ,  Md Tofizur Rahman

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.

公开(公告)号：US11276730B2

公开(公告)日：2022-03-15

申请号：US16246360

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Christopher Wiegand ,  Tofizur Rahman ,  Noriyuki Sato ,  Gary Allen ,  James Pellegren ,  Angeline Smith ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Benjamin Buford ,  Ian Young

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/14 ,  H01L43/08 ,  H01L43/10

Abstract: A perpendicular spin orbit memory device includes a first electrode having a magnetic material and platinum and a material layer stack on a portion of the first electrode. The material layer stack includes a free magnet, a fixed magnet above the first electrode, a tunnel barrier between the free magnet and the fixed magnet and a second electrode coupled with the fixed magnet.