公开(公告)号：US20240222113A1

公开(公告)日：2024-07-04

申请号：US18091279

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Carl H. Naylor ,  Kirby Maxey ,  Kevin OBrien ,  Chelsey Dorow ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Matthew Metz ,  Scott B. Clendenning ,  Mahmut Sami Kavrik ,  Chia-Ching Lin ,  Ande Kitamura

IPC: H01L21/02 ,  H01L21/04 ,  H01L23/31

CPC classification number: H01L21/02568 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/045 ,  H01L23/3171

Abstract: Integrated circuit (IC) structures comprising transistors with metal chalcogenide channel material synthesized on a workpiece comprising a Group IV crystal. Prior to synthesis of the metal chalcogenide material, a passivation material is formed over the Group IV crystal to limit exposure of the substrate to the growth precursor gas(es) and thereby reduce a quantity of chalcogen species subsequently degassed from the workpiece. The passivation material may be applied to the front side, back side, and/or edge of a workpiece. The passivation material may be sacrificial or retained as a permanent feature of an IC structure. The passivation material may be advantageously amorphous and/or a compound comprising at least one of a metal or nitrogen that is good diffusion barrier and thermally stable at the metal chalcogenide synthesis temperatures.