公开(公告)号：US11195575B1

公开(公告)日：2021-12-07

申请号：US16946527

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Jaydip Bharatkumar Patel ,  Everardo Flores, III ,  Khaled Hasnat ,  Max F. Hineman

IPC: G11C11/4099 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/408 ,  G11C5/02

Abstract: A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.

公开(公告)号：US10854746B2

公开(公告)日：2020-12-01

申请号：US16190135

申请日：2018-11-13

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Khaled Hasnat ,  Krishna Parat

IPC: H01L29/792 ,  H01L29/78 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/04 ,  H01L27/11582 ,  H01L29/16 ,  H01L27/1157 ,  H01L21/28

Abstract: A memory structure can include a conductive channel, a charge storage structure adjacent to the conductive channel, and a strain-inducing layer adjacent to the conductive channel on a side opposite the charge storage structure. The strain-inducing layer can have a higher coefficient of thermal expansion (CTE) than the conductive channel.

公开(公告)号：US10651153B2

公开(公告)日：2020-05-12

申请号：US16011139

申请日：2018-06-18

Applicant: Intel Corporation

Inventor： Richard Fastow ,  Khaled Hasnat ,  Prashant Majhi ,  Owen Jungroth

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L25/065 ,  G11C16/08 ,  H01L23/00 ,  G11C16/04 ,  H01L27/11573 ,  H01L27/06 ,  H01L27/11575 ,  H01L27/11582 ,  H01L25/00 ,  G11C5/02

Abstract: Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile storage device includes a first die including a 3D array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die including a second 3D array of non-volatile storage cells is vertically stacked and bonded with the first die. At least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die.

公开(公告)号：US10515973B2

公开(公告)日：2019-12-24

申请号：US15828039

申请日：2017-11-30

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Owen W. Jungroth ,  David S. Meyaard ,  Khaled Hasnat

IPC: H01L27/11531 ,  G11C16/04 ,  H01L27/11551 ,  H01L27/11573 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.

公开(公告)号：US20190043873A1

公开(公告)日：2019-02-07

申请号：US16122266

申请日：2018-09-05

Applicant: Intel Corporation

Inventor： Khaled Hasnat ,  Prashant Majhi ,  Deepak Thimmegowda

IPC: H01L27/11529 ,  H01L27/11573 ,  H01L29/786 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11531

Abstract: Embodiments of the present disclosure are directed towards a memory device with vertical string drivers, in accordance with some embodiments. In one embodiment, the memory device includes a plurality of wordlines formed in a stack of multiple tiers. The device further includes a semiconductor layer disposed on top of the plurality of wordlines. The device further includes a plurality of string drivers disposed in the semiconductor layer substantially perpendicular to the tier stack of the plurality of wordlines. The semiconductor layer provides respective gate connections for the plurality of string drivers. In some embodiments, the semiconductor layer may be fabricated of polysilicon. Other embodiments may be described and/or claimed.

公开(公告)号：US11500446B2

公开(公告)日：2022-11-15

申请号：US16586957

申请日：2019-09-28

Applicant: Intel Corporation

Inventor： Richard Fastow ,  Shankar Natarajan ,  Chang Wan Ha ,  Chee Law ,  Khaled Hasnat ,  Chuan Lin ,  Shafqat Ahmed

IPC: G06F1/32 ,  G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G06F1/3234

Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

公开(公告)号：US20210407582A1

公开(公告)日：2021-12-30

申请号：US16946527

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Jaydip Bharatkumar Patel ,  Everardo Flores, III ,  Khaled Hasnat ,  Max F. Hineman

IPC: G11C11/4099 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4074 ,  G11C5/02

Abstract: A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.

公开(公告)号：US10923450B2

公开(公告)日：2021-02-16

申请号：US16437445

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Richard Fastow ,  Khaled Hasnat ,  Prashant Majhi ,  Owen W. Jungroth ,  Krishna Parat

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11573 ,  H01L25/18

Abstract: An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.

公开(公告)号：US10861867B2

公开(公告)日：2020-12-08

申请号：US16021550

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Khaled Hasnat ,  Prashant Majhi ,  Krishna Parat

IPC: H01L27/11582 ,  H01L23/532 ,  H01L29/49 ,  H01L21/768 ,  H01L29/51 ,  H01L23/528 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L21/3105 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/02

Abstract: Embodiments of the present disclosure are directed towards techniques to provide a memory device with reduced capacitance. In one embodiment, a memory array is formed in a die, and includes one or more pillars and a plurality of wordlines coupled with the one or more pillars. Adjacent wordlines of the plurality of wordlines are separated by respective dielectric layers, which may include components, to reduce capacitance of the plurality of wordlines. The components comprise air gaps or low-k dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20220190029A1

公开(公告)日：2022-06-16

申请号：US17118367

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Derchang Kau ,  Prashant Majhi ,  Khaled Hasnat

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory structure includes a plurality of memory cells between a first and a second terminal and a pair of first conductors within a first tier, where individual ones of the first conductors are coupled to the first terminal of a first adjacent pair of memory cells in a first row orthogonal to the first conductors. The memory structure further includes a pair of second conductors within a second tier and parallel to the first conductors, where individual ones of the second conductors are coupled to the first terminal of a second adjacent pair of memory cells in a second row. The memory structure further includes a third conductor between the first and second tiers, and between each of the pair of the first conductors and the pair of the second conductors. The third conductor is coupled to second terminals of both the first and second adjacent pairs of memory cells.