公开(公告)号：US10817042B2

公开(公告)日：2020-10-27

申请号：US16144538

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Kinchit Desai ,  Sanjeev Jahagirdar ,  Prasoonkumar Surti ,  Joydeep Ray

IPC: G06F1/3237 ,  G06N3/04 ,  G06N3/08 ,  G06F1/3234 ,  G06F1/3206

Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.

公开(公告)号：US20180286006A1

公开(公告)日：2018-10-04

申请号：US15477249

申请日：2017-04-03

Applicant: INTEL CORPORATION

Inventor： Nikos Kaburlasos ,  Kinchit Desai ,  Sanjeev S. Jahagirdar

IPC: G06T1/20 ,  G06T1/60

Abstract: An apparatus for tile reuse in imaging is described herein. The apparatus a memory, a line based processing system, a block based processing system, and a tile reuse indicator. The memory is to store imaging data. The line-based processing system is to process lines of imaging data and store the processed data in memory and the block-based processing system is to process blocks of the line based processed imaging data and storing the processed data in memory. The tile reuse indicator is to determine an unchanged tile of the imaging data, and in response to an unchanged tile prevent further processing of the unchanged tile.