公开(公告)号：US11074188B2

公开(公告)日：2021-07-27

申请号：US16278509

申请日：2019-02-18

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Alaa R. Alameldeen ,  Lidia Warnes ,  Andy M. Rudoff ,  Muthukumar P. Swaminathan

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/02 ,  G06F12/0893

Abstract: A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

公开(公告)号：US11573722B2

公开(公告)日：2023-02-07

申请号：US16987057

申请日：2020-08-06

Applicant: Intel Corporation

Inventor： Rasika Subramanian ,  Lidia Warnes ,  Francesc Guim Bernat ,  Mark A. Schmisseur ,  Durgesh Srivastava

IPC: G06F3/06

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to provide an interface to a pooled memory that is configured as a combination of local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, allocate respective memory portions of the pooled memory to respective tenants, associate respective memory balloons with the respective tenants that correspond to the allocated respective memory portions, and manage the respective memory balloons based on the respective tenants and two or more memory tiers associated with the pooled memory. Other embodiments are disclosed and claimed.

公开(公告)号：US10402124B2

公开(公告)日：2019-09-03

申请号：US15474044

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Mark Schmisseur ,  Karthik Kumar ,  Thomas Willhalm ,  Lidia Warnes

IPC: G06F3/06 ,  G06F9/50

Abstract: The present disclosure relates to a dynamically composable computing system. The dynamically composable computing system comprises at least one compute sled including a set of respective local computing hardware resources; a plurality of disaggregated memory modules; at least one disaggregated memory acceleration logic configured to perform one or more predefined computations on data stored in one or more of the plurality of disaggregated memory modules; and a resource manager module configured to assemble a composite computing node by associating, in accordance with requirements of a user, at least one of the plurality of disaggregated memory modules with the disaggregated memory acceleration logic to provide at least one accelerated disaggregated memory module and connecting the least one accelerated disaggregated memory module to the compute sled.

公开(公告)号：US20180284996A1

公开(公告)日：2018-10-04

申请号：US15474044

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Mark Schmisseur ,  Karthik Kumar ,  Thomas Willhalm ,  Lidia Warnes

IPC: G06F3/06

CPC classification number: G06F3/067 ,  G06F3/0605 ,  G06F3/0631 ,  G06F9/50

Abstract: The present disclosure relates to a dynamically composable computing system. The dynamically composable computing system comprises at least one compute sled including a set of respective local computing hardware resources; a plurality of disaggregated memory modules; at least one disaggregated memory acceleration logic configured to perform one or more predefined computations on data stored in one or more of the plurality of disaggregated memory modules; and a resource manager module configured to assemble a composite computing node by associating, in accordance with requirements of a user, at least one of the plurality of disaggregated memory modules with the disaggregated memory acceleration logic to provide at least one accelerated disaggregated memory module and connecting the least one accelerated disaggregated memory module to the compute sled.

公开(公告)号：US11983408B2

公开(公告)日：2024-05-14

申请号：US18142942

申请日：2023-05-03

Applicant: Intel Corporation

Inventor： Rasika Subramanian ,  Lidia Warnes ,  Francesc Guim Bernat ,  Mark A. Schmisseur ,  Durgesh Srivastava

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0631 ,  G06F3/0665 ,  G06F3/0673

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other embodiments are disclosed and claimed.

公开(公告)号：US20220012112A1

公开(公告)日：2022-01-13

申请号：US17485335

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Rita H. Wouhaybi ,  Patricia M. Mwove Shaffer ,  Aline C. Kenfack Sadate ,  Lidia Warnes

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06N20/00

Abstract: A system for generating a robustness score for hardware components, nodes, and clusters of nodes in a computing infrastructure is provided. The system includes a memory and at least one processing device coupled to the memory. The processing device is to obtain first telemetry data associated with a selected portion of a computing infrastructure, and the selected portion includes a first node and a first hardware component. The processing device is further to obtain first metadata associated with the selected portion, input one or more telemetry inputs corresponding to the first telemetry data into a machine learning model, input one or more metadata inputs corresponding to the first metadata into the machine learning model, and generate, from the machine learning model, a first robustness score for the first hardware component representing a health state of the first hardware component.

公开(公告)号：US20200326861A1

公开(公告)日：2020-10-15

申请号：US16914124

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Rasika Subramanian ,  Lidia Warnes ,  Francesc Guim Bernat ,  Mark A. Schmisseur ,  Durgesh Srivastava

IPC: G06F3/06

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other embodiments are disclosed and claimed.

公开(公告)号：US20230333738A1

公开(公告)日：2023-10-19

申请号：US18142942

申请日：2023-05-03

Applicant: Intel Corporation

Inventor： Rasika Subramanian ,  Lidia Warnes ,  Francesc Guim Bernat ,  Mark A. Schmisseur ,  Durgesh Srivastava

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0631 ,  G06F3/0665 ,  G06F3/0673

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other embodiments are disclosed and claimed.

公开(公告)号：US11693721B2

公开(公告)日：2023-07-04

申请号：US17485335

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Rita H. Wouhaybi ,  Patricia M. Mwove Shaffer ,  Aline C. Kenfack Sadate ,  Lidia Warnes

IPC: G06F11/34 ,  G06F11/00 ,  G06N20/00 ,  G06F11/30 ,  G06F11/07

CPC classification number: G06F11/008 ,  G06F11/0709 ,  G06F11/3006 ,  G06F11/3447 ,  G06N20/00

Abstract: A system for generating a robustness score for hardware components, nodes, and clusters of nodes in a computing infrastructure is provided. The system includes a memory and at least one processing device coupled to the memory. The processing device is to obtain first telemetry data associated with a selected portion of a computing infrastructure, and the selected portion includes a first node and a first hardware component. The processing device is further to obtain first metadata associated with the selected portion, input one or more telemetry inputs corresponding to the first telemetry data into a machine learning model, input one or more metadata inputs corresponding to the first metadata into the machine learning model, and generate, from the machine learning model, a first robustness score for the first hardware component representing a health state of the first hardware component.

公开(公告)号：US11681439B2

公开(公告)日：2023-06-20

申请号：US16914124

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Rasika Subramanian ,  Lidia Warnes ,  Francesc Guim Bernat ,  Mark A. Schmisseur ,  Durgesh Srivastava

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0631 ,  G06F3/0665 ,  G06F3/0673

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other embodiments are disclosed and claimed.