公开(公告)号：US12101479B2

公开(公告)日：2024-09-24

申请号：US16828650

申请日：2020-03-24

Applicant: INTEL CORPORATION

Inventor： Jason Tanner ,  Sergei Plotnikov ,  Mark Buxton

IPC: H04N19/55 ,  H04N19/119 ,  H04N19/124 ,  H04N19/14 ,  H04N19/172 ,  H04N19/176

CPC classification number: H04N19/119 ,  H04N19/124 ,  H04N19/14 ,  H04N19/172 ,  H04N19/176

Abstract: Techniques related to parallel block video coding using an adaptive wavefront split are discussed. Such techniques include adaptively applying a wavefront split in a video frame based on a frame level quantization parameter of the video frame, an encode duration of a previous frame, and/or image content of the video frame.

公开(公告)号：US09235415B2

公开(公告)日：2016-01-12

申请号：US14533474

申请日：2014-11-05

Applicant: Intel Corporation

Inventor： Cristina Anderson ,  Mark Buxton ,  Doron Orenstein ,  Robert Valentine

IPC: G06F7/76 ,  G06F9/315 ,  G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30032 ,  G06F7/76 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F12/0875 ,  G06F2212/452

Abstract: In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an operation between at least two of the control values so that selected portions of the first and second source operands or a predetermined value can be stored into elements of a destination. Multiple permute instructions may be combined to perform efficient table lookups. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括接收置换指令，第一和第二源操作数和控制值的逻辑，以及基于至少两个控制值之间的操作执行置换操作，使得第一 并且可以将第二源操作数或预定值存储到目的地的元素中。 可以组合多个置换指令以执行有效的表查找。 描述和要求保护其他实施例。

公开(公告)号：US10146536B2

公开(公告)日：2018-12-04

申请号：US15885269

申请日：2018-01-31

Applicant: Intel Corporation

Inventor： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC: G06F9/30 ,  G06F7/02 ,  G06F9/38 ,  G06F12/0875

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

公开(公告)号：US20180181395A1

公开(公告)日：2018-06-28

申请号：US15885269

申请日：2018-01-31

Applicant: Intel Corporation

Inventor： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC: G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

公开(公告)号：US09898285B2

公开(公告)日：2018-02-20

申请号：US15345221

申请日：2016-11-07

Applicant: Intel Corporation

Inventor： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC: G06F7/50 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

公开(公告)号：US09489198B2

公开(公告)日：2016-11-08

申请号：US15015991

申请日：2016-02-04

Applicant: Intel Corporation

Inventor： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC: G06F7/50 ,  G06F9/30 ,  G06F7/02 ,  G06F9/38

CPC classification number: G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

公开(公告)号：US20200228801A1

公开(公告)日：2020-07-16

申请号：US16828650

申请日：2020-03-24

Applicant: INTEL CORPORATION

Inventor： Jason Tanner ,  Sergei Plotnikov ,  Mark Buxton

IPC: H04N19/119 ,  H04N19/124 ,  H04N19/172 ,  H04N19/14 ,  H04N19/176

Abstract: Techniques related to parallel block video coding using an adaptive wavefront split are discussed. Such techniques include adaptively applying a wavefront split in a video frame based on a frame level quantization parameter of the video frame, an encode duration of a previous frame, and/or image content of the video frame.

公开(公告)号：US20170364476A1

公开(公告)日：2017-12-21

申请号：US15640395

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Ronen Zohar ,  Mark Seconi ,  Rajesh Parthasarathy ,  Srinivas Chennupaty ,  Mark Buxton ,  Chuck Desylva ,  Mohammad Abdallah

IPC: G06F17/10 ,  G06F7/48 ,  G06F7/544 ,  G06F9/30

CPC classification number: G06F17/10 ,  G06F7/48 ,  G06F7/5443 ,  G06F9/3001

Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

公开(公告)号：US20170161068A1

公开(公告)日：2017-06-08

申请号：US15345221

申请日：2016-11-07

Applicant: Intel Corporation

Inventor： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC: G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

公开(公告)号：US20150212816A1

公开(公告)日：2015-07-30

申请号：US14684412

申请日：2015-04-12

Applicant: Intel Corporation

Inventor： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC: G06F9/30

CPC classification number: G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Abstract translation: 一种用于在处理器中包括用于对打包或未打包的数据执行逻辑比较和分支支持操作的指令的方法和装置。 在一个实施例中，指令解码逻辑解码用于执行单元对包括逻辑比较的打包数据元素进行操作的指令。 包括128位打包数据寄存器的寄存器文件存储打包的单精度浮点数（SPFP）和压缩整数数据元素。 逻辑比较可以包括SPFP数据元素的比较和整数数据元素的比较，并且设置至少一个位以指示结果。 基于这些比较，采取分支支持行动。 这种分支支持动作可以包括设置至少一个比特，响应于分支指令又可以由分支单元利用该比特。 或者，分支支持动作可以包括分支到指示的目标代码位置。