公开(公告)号：US20180039593A1

公开(公告)日：2018-02-08

申请号：US15784607

申请日：2017-10-16

Applicant: Intel Corporation

Inventor： Mark Debbage ,  Yatin M. Mutha

IPC: G06F13/372 ,  G06F13/16 ,  G06F13/362 ,  G06F5/06 ,  G06F13/42 ,  G06F13/28 ,  G06F15/78

CPC classification number: G06F13/372 ,  G06F5/065 ,  G06F13/128 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/3625 ,  G06F13/4221 ,  G06F13/4265 ,  G06F13/4282 ,  G06F15/167 ,  G06F15/7807 ,  G06F2205/067 ,  G06F2213/0026 ,  G06F2213/2806 ,  G06F2213/36

Abstract: Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

公开(公告)号：US20150378737A1

公开(公告)日：2015-12-31

申请号：US14316670

申请日：2014-06-26

Applicant: Intel Corporation

Inventor： Mark Debbage ,  Yatin M. Mutha

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F12/0875 ,  G06F5/065 ,  G06F5/14 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3855 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/4282 ,  G06F2205/067 ,  G06F2205/126 ,  G06F2212/452 ,  G06F2213/0026

Abstract: Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received at a processor supporting out of order execution. The PIO write instructions are received in an original order and executed out of order, with each PIO write instruction writing a store unit of data to a store buffer or a store block of data to the store buffer. Logic is provided for the store buffer to detect when store blocks are filled, resulting in the data in those store blocks being drained via PCIe posted writes that are written to send blocks in the PIO send memory at addresses defined by the PIO write instructions. Logic is employed for detecting the fill size of packets and when a packet's send blocks have been filled, enabling the packet data to be eligible for egress.

Abstract translation: 使用优化的PIO写入序列发送数据包的方法和设备，无故障。 在支持无序执行的处理器处接收到用于将分组数据写入PIO发送存储器的编程输入/输出（PIO）写入指令的顺序。 PIO写指令以原始顺序接收，并按顺序执行，每个PIO写指令将存储单元写入存储缓冲区或存储数据块到存储缓冲区。 逻辑被提供给存储缓冲器以检测何时存储块被填充，导致这些存储块中的数据通过PCIe写入被写入PIO发送存储器中的PIO发送存储器中由PIO写入指令定义的地址而被排出。 逻辑用于检测分组的填充大小，并且当分组的发送块已经被填充时，使分组数据符合出口条件。

公开(公告)号：US12212502B2

公开(公告)日：2025-01-28

申请号：US17084526

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Mark Debbage ,  Robert Southworth ,  Arvind Srinivasan ,  Cheolmin Park ,  Todd Rimmer ,  Brian S. Hausauer

IPC: H04L47/34 ,  H04L1/1607 ,  H04L47/125

Abstract: Examples described herein relate to technologies for reliable packet transmission. In some examples, a network interface includes circuitry to: receive a request to transmit a packet to a destination device, select a path for the packet, provide a path identifier identifying one of multiple paths from the network interface to a destination and Path Sequence Number (PSN) for the packet, wherein the PSN is to identify a packet transmission order over the selected path, include the PSN in the packet, and transmit the packet. In some examples, if the packet is a re-transmit of a previously transmitted packet, the circuitry is to: select a path for the re-transmit packet, and set a PSN of the re-transmit packet that is a current packet transmission number for the selected path for the re-transmit packet. In some examples, a network interface includes circuitry to process a received packet to at least determine a Path Sequence Number (PSN) for the received packet, wherein the PSN is to provide an order of packet transmissions for a path associated with the received packet, process a second received packet to at least determine its PSN, and based on the PSN of the second received packet not being a next sequential value after the PSN of the received packet, cause transmission of a re-transmit request to a sender of the packet and the second packet.

公开(公告)号：US12137001B2

公开(公告)日：2024-11-05

申请号：US17483668

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Mark Debbage ,  Bruce G. Warren

IPC: H04L1/1607 ,  H04L49/90 ,  H04L69/22

Abstract: Examples described herein relate to a network interface device that includes circuitry to track one or more gaps in received packet sequence numbers using data and circuitry to indicate to a sender of packets non-delivered packets to identify a range of delivered packets. In some examples, the data identifies delivered packets and undelivered packets for one or more connections. In some examples, to indicate to a sender of packets non-delivered packets to identify a range of delivered packets, the circuitry is to provide negative acknowledgement sequence range indicating a start and end of non-delivered packets.

公开(公告)号：US09734077B2

公开(公告)日：2017-08-15

申请号：US15277527

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Mark Debbage ,  Yatin M. Mutha

IPC: G06F12/08 ,  G06F13/42 ,  G06F5/14 ,  G06F13/28 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F5/06

CPC classification number: G06F12/0875 ,  G06F5/065 ,  G06F5/14 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3855 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/4282 ,  G06F2205/067 ,  G06F2205/126 ,  G06F2212/452 ,  G06F2213/0026

Abstract: Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received at a processor supporting out of order execution. The PIO write instructions are received in an original order and executed out of order, with each PIO write instruction writing a store unit of data to a store buffer or a store block of data to the store buffer. Logic is provided for the store buffer to detect when store blocks are filled, resulting in the data in those store blocks being drained via PCIe posted writes that are written to send blocks in the PIO send memory at addresses defined by the PIO write instructions. Logic is employed for detecting the fill size of packets and when a packet's send blocks have been filled, enabling the packet data to be eligible for egress.

公开(公告)号：US10044626B2

公开(公告)日：2018-08-07

申请号：US14757993

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Keith Underwood ,  Charles Giefer ,  Mark Debbage ,  Karl P. Brummel ,  Nathan Miller ,  Bruce Pirie

IPC: H04L12/801 ,  H04L12/807 ,  H04L12/869 ,  H04L1/16 ,  H04L1/18 ,  H04L29/06

Abstract: In an embodiment, an out-of-order, reliable, end-to-end protocol is provided that can enable direct user-level data placement and atomic operations between nodes of a multi-node network. The protocol may be optimized for low-loss environments such as High Performance Computing (HPC) applications, and may enable loss detection and de-duplication of packets through the use of a robust window state manager at a target node. A multi-node network implementing the protocol may have increased system reliability, packet throughput, and increased tolerance for adaptively routed traffic, while still allowing atomic operations to be idempotently applied directly to a user memory location.

公开(公告)号：US09792235B2

公开(公告)日：2017-10-17

申请号：US15285825

申请日：2016-10-05

Applicant: Intel Corporation

Inventor： Mark Debbage ,  Yatin M. Mutha

IPC: G06F13/36 ,  G06F13/372 ,  G06F13/42 ,  G06F13/28 ,  G06F5/06 ,  G06F13/16 ,  G06F13/362 ,  G06F15/78

CPC classification number: G06F13/372 ,  G06F5/065 ,  G06F13/128 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/3625 ,  G06F13/4221 ,  G06F13/4265 ,  G06F13/4282 ,  G06F15/167 ,  G06F15/7807 ,  G06F2205/067 ,  G06F2213/0026 ,  G06F2213/2806 ,  G06F2213/36

Abstract: Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

公开(公告)号：US09785359B2

公开(公告)日：2017-10-10

申请号：US15054325

申请日：2016-02-26

Applicant: Intel Corporation

Inventor： Yatin Mutha ,  Mark Debbage

IPC: G06F3/06 ,  H04L12/883 ,  H04L12/879 ,  H04L12/861 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0656 ,  G06F3/067 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2213/0026 ,  H04L49/901 ,  H04L49/9015 ,  H04L49/9068

Abstract: Methods and apparatus for sending packets using optimized PIO write sequences without sfences and out-of-order credit returns. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received by a processor in an original order and executed out of order, resulting in the packet data being written to send blocks in the PIO send memory out of order, while the packets themselves are stored in sequential order once all of the packet data is written. The packets are egressed out of order by egressing packet data contained in the send blocks to an egress block using a non-sequential packet order that is different than the sequential packet order. In conjunction with egressing the packets, corresponding credits are returned in the non-sequential packet order. A block list comprising a linked list and a free list are used to facilitate out-of-order packet egress and corresponding out-of-order credit returns.

公开(公告)号：US09588899B2

公开(公告)日：2017-03-07

申请号：US15255284

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Mark Debbage ,  Yatin M. Mutha

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F12/0875 ,  G06F5/065 ,  G06F5/14 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3855 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/4282 ,  G06F2205/067 ,  G06F2205/126 ,  G06F2212/452 ,  G06F2213/0026

Abstract: Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received at a processor supporting out of order execution. The PIO write instructions are received in an original order and executed out of order, with each PIO write instruction writing a store unit of data to a store buffer or a store block of data to the store buffer. Logic is provided for the store buffer to detect when store blocks are filled, resulting in the data in those store blocks being drained via PCIe posted writes that are written to send blocks in the PIO send memory at addresses defined by the PIO write instructions. Logic is employed for detecting the fill size of packets and when a packet's send blocks have been filled, enabling the packet data to be eligible for egress.

Abstract translation: 使用优化的PIO写入序列发送数据包的方法和设备，无故障。 在支持无序执行的处理器处接收到用于将分组数据写入PIO发送存储器的编程输入/输出（PIO）写入指令的顺序。 PIO写指令以原始顺序接收，并按顺序执行，每个PIO写指令将存储单元写入存储缓冲区或存储数据块到存储缓冲区。 逻辑被提供给存储缓冲器以检测何时存储块被填充，导致这些存储块中的数据通过PCIe写入被写入PIO发送存储器中的PIO发送存储器中由PIO写入指令定义的地址而被排出。 逻辑用于检测分组的填充大小，并且当分组的发送块已经被填充时，使分组数据符合出口条件。

公开(公告)号：US20150378953A1

公开(公告)日：2015-12-31

申请号：US14316689

申请日：2014-06-26

Applicant: Intel Corporation

Inventor： Mark Debbage ,  Yatin M. Mutha

IPC: G06F13/42 ,  G06F13/16 ,  G06F13/28 ,  G06F13/362

CPC classification number: G06F13/372 ,  G06F5/065 ,  G06F13/128 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/3625 ,  G06F13/4221 ,  G06F13/4265 ,  G06F13/4282 ,  G06F15/167 ,  G06F15/7807 ,  G06F2205/067 ,  G06F2213/0026 ,  G06F2213/2806 ,  G06F2213/36

Abstract: Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

Abstract translation: 用于实现分组发送的优化信用回报机制的方法和装置。 编程输入/输出（PIO）发送存储器被划分成多个发送上下文，每个发送上下文包括一个存储器缓冲器，该存储器缓冲器包括被配置为存储分组数据的多个发送块。 使用FIFO语义的存储方案通过与相应的FIFO插槽相关联的每个发送块来实现。 响应于接收到写入发送块的分组数据并检测那些发送块中的数据已经从发送上下文中被发现，检测到相应的释放的FIFO时隙，并且确定没有返回信用返回标记的最低时隙。 然后确定从最低时隙的释放时隙序列中的最高时隙，并返回相应的信用回报标记。 在一个实施例中，对于每个发送上下文实现绝对信用回报计数，其中通过写入PIO发送存储器的软件跟踪相关联的绝对信用发送计数，其中两个绝对信用计数用于流量控制。