公开(公告)号：US12093694B2

公开(公告)日：2024-09-17

申请号：US17214693

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Mathew Lowes ,  Jonathan Combs ,  Martin Licht

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3804 ,  G06F9/3856

Abstract: Techniques and mechanisms for providing branch prediction information to facilitate instruction decoding by a processor. In an embodiment, entries of a branch prediction table (BTB) each identify, for a corresponding instruction, whether a prediction based on the instruction (if any) is eligible to be communicated, with another prediction, in a single fetch cycle. A branch prediction unit of the processor determines a linear address of a fetch region which is under consideration, and performs a search of the BTB based on the linear address. A result of the search is evaluated to detect for any hit entry which indicates a double prediction eligibility. In another embodiment, where it is determined that double prediction eligibility is indicated for an earliest one the instructions represented by the hit entries, multiple predictions are communicated in a single fetch cycle.

公开(公告)号：US20240220253A1

公开(公告)日：2024-07-04

申请号：US18148397

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Mathew Lowes ,  Martin J. Licht ,  Jonathan D. Combs

IPC: G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/30047 ,  G06F12/0875

Abstract: Techniques for implementing a variable width unaligned fetch for instructions are described. In certain examples, a hardware processor core includes fetch circuitry to perform a single fetch operation to fetch from a paged memory: (i) a multiple cache line width of instruction data, between a minimum width that is greater than one cache line and a maximum width that is a plurality of cache lines, when the multiple cache line width of the instruction data does not include a page boundary of the paged memory, and (ii) less than or equal to one cache line width of the instruction data when the multiple cache line width of the instruction data does include the page boundary of the paged memory; decoder circuitry to decode a single instruction, comprising an opcode, from the instruction data into a decoded instruction; and execution circuitry to execute the decoded instruction according to the opcode.

公开(公告)号：US20230409335A1

公开(公告)日：2023-12-21

申请号：US17843179

申请日：2022-06-17

Applicant: Intel Corporation

Inventor： Mathew Lowes ,  Jared Warner Stark, IV ,  Martin Licht

IPC: G06F9/38 ,  G06F9/32

CPC classification number: G06F9/3844 ,  G06F9/321 ,  G06F9/3806

Abstract: Techniques for selective disable of history-based predictors on mode transitions are described. An example apparatus comprises first circuitry to provide a history-based prediction, and second circuitry coupled to the first circuitry to selectively block and unblock a prediction from the first circuitry after a mode transition. Other examples are disclosed and claimed.

公开(公告)号：US20230401067A1

公开(公告)日：2023-12-14

申请号：US17840029

申请日：2022-06-14

Applicant: Intel Corporation

Inventor： Mathew Lowes ,  Martin Licht ,  Jonathan Combs

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/3016

Abstract: In one embodiment, an apparatus comprises: a branch prediction circuit to predict whether a branch is to be taken; a fetch circuit, in a single fetch cycle, to send a first portion of a fetch region of instructions to a first decode cluster and send a second portion of the fetch region to the second decode cluster; the first decode cluster comprising a first plurality of decode circuits to decode one or more instructions in the first portion of the fetch region; and the second decode cluster comprising a second plurality of decode circuits to decode one or more other instructions in the second portion of the fetch region. Other embodiments are described and claimed.

公开(公告)号：US20220405102A1

公开(公告)日：2022-12-22

申请号：US17352671

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Mathew Lowes ,  Martin Licht

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/30

Abstract: An embodiment of an integrated circuit may comprise a return stack buffer (RSB), a speculative return stack buffer (SRSB), and circuitry coupled to the RSB and the SRSB, the circuitry to track a count until the SRSB is empty at a time of a prediction by a branch prediction unit, and return an output from the branch prediction unit that corresponds to one of the RSB and the SRSB based at least in part on the count until the SRSB is empty. Other embodiments are disclosed and claimed.

公开(公告)号：US20220318020A1

公开(公告)日：2022-10-06

申请号：US17214693

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Mathew Lowes ,  Jonathan Combs ,  Martin Licht

IPC: G06F9/38

Abstract: Techniques and mechanisms for providing branch prediction information to facilitate instruction decoding by a processor. In an embodiment, entries of a branch prediction table (BTB) each identify, for a corresponding instruction, whether a prediction based on the instruction (if any) is eligible to be communicated, with another prediction, in a single fetch cycle. A branch prediction unit of the processor determines a linear address of a fetch region which is under consideration, and performs a search of the BTB based on the linear address. A result of the search is evaluated to detect for any hit entry which indicates a double prediction eligibility. In another embodiment, where it is determined that double prediction eligibility is indicated for an earliest one the instructions represented by the hit entries, multiple predictions are communicated in a single fetch cycle.