公开(公告)号：US20230176987A1

公开(公告)日：2023-06-08

申请号：US18082485

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Patrick Connor ,  Matthew A. JARED ,  Duke C. HONG ,  Elizabeth M. KAPPLER ,  Chris Pavlas ,  Scott P. Dubal

IPC: G06F13/40

CPC classification number: G06F13/4022

Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.