公开(公告)号：US20250112185A1

公开(公告)日：2025-04-03

申请号：US18374515

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Michael Baker ,  Seyed Hadi Zandavi ,  Yi Shi ,  Feras Eid

IPC: H01L23/00

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by superhydrophobic structures that have a contact angle not less than 150 degrees. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. The liquid droplet is pinned to the hybrid bonding regions by the superhydrophobic structures. A hybrid bond is formed by evaporating the droplet and a subsequent anneal.

公开(公告)号：US20230317660A1

公开(公告)日：2023-10-05

申请号：US17710518

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Zhaozhi Li ,  Feras Eid ,  Michael Baker ,  Wenhao Li ,  Pilin Liu ,  Johanna Swan

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/06 ,  H01L24/81 ,  H01L24/16 ,  H01L2224/1403 ,  H01L2224/10145 ,  H01L2224/0401 ,  H01L2224/81203 ,  H01L2224/16227 ,  H01L2224/14177

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate having one or more solder structures. A first set of solder structures is located in a peripheral region of the substrate and a second set of solder structures is located in a central region of the substrate. A height of individual ones of the second set of solder structures is greater than a height of individual ones of the first set of solder structures. A die having a first side and a second side includes one or more conductive die pads on the first side, where individual ones of the conductive die pads are on individual ones of the first set solder structures and on individual ones of the second set solder structures. A die backside layer is on the second side of the die.

公开(公告)号：US20230317545A1

公开(公告)日：2023-10-05

申请号：US17710507

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Pilin Liu ,  Feras Eid ,  Michael Baker ,  Wenhao Li ,  Zhaozhi Li

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/367 ,  H01L24/16 ,  H01L24/17 ,  H01L24/08 ,  H01L24/09 ,  H01L24/81 ,  H01L23/3732 ,  H01L2924/37001 ,  H01L2924/3511 ,  H01L2224/81203 ,  H01L2224/10155 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16237 ,  H01L2224/16014 ,  H01L2224/16013 ,  H01L2224/16057 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17132 ,  H01L2224/17133 ,  H01L2224/0801 ,  H01L2224/0903 ,  H01L2224/09104 ,  H01L2224/08113

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.

公开(公告)号：US20250112200A1

公开(公告)日：2025-04-03

申请号：US18374559

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Kimin Jun ,  Feras Eid ,  Thomas Sounart ,  Yi Shi ,  Shawna Liff ,  Johanna Swan ,  Michael Baker ,  Bhaskar Jyoti Krishnatreya ,  Chien-An Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.

公开(公告)号：US20250112199A1

公开(公告)日：2025-04-03

申请号：US18374520

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Feras Eid ,  Adel Elsherbini ,  Yi Shi ,  Michael Baker ,  Kimin Jun ,  Wenhao Li

IPC: H01L23/00 ,  H01L25/065

Abstract: Hybrid bonded multi-level die stacks, related apparatuses, systems, and methods of fabrication are disclosed. First-level integrated circuit (IC) dies and a base substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet followed by anneal. Hybrid bonding regions of second-level IC dies are similarly bonded to hybrid bonding regions on backsides of the first-level IC dies. This is repeated for any number of subsequent levels of IC dies. IC structures including the bonded IC dies and portions of the base substrate are segmented and assembled.

公开(公告)号：US20250112177A1

公开(公告)日：2025-04-03

申请号：US18374516

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Thomas Sounart ,  Yi Shi ,  Michael Baker ,  Adel Elsherbini ,  Kimin Jun ,  Xavier Brun ,  Wenhao Li

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/786

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die backside surface and a surface of a structural substrate each include bonding regions surrounded by hydrophobic structures. A liquid droplet is applied to the die or structural substrate bonding region and the die is placed on the bonding region of the structural substrate. Capillary forces cause the die to self-align to the bonding region, and a bond is formed by evaporating the liquid and subsequent anneal. A hybrid bond is then formed between the opposing active surface of the die and a base substrate using wafer-to-wafer bonding. IC structures including the IC die and portions of the structural substrate and base substrate are segmented from the bonded wafers and assembled.

公开(公告)号：US20230317676A1

公开(公告)日：2023-10-05

申请号：US17711926

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Michael Baker ,  Feras Eid ,  Wenhao Li ,  Zhaozhi Li ,  Pilin Liu

IPC: H01L23/00 ,  B23K20/02

CPC classification number: H01L24/75 ,  H01L24/81 ,  B23K20/023 ,  H01L2224/05647 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/75983 ,  H01L2224/75984 ,  H01L2224/75985 ,  H01L2224/75312 ,  H01L2224/75252 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/75253 ,  B23K2101/40

Abstract: Microelectronic die package structures formed according to some embodiments may include a thermal compression bonding (TCB) assembly including a bond head with a first thermal zone separated from a second thermal zone by a thermal separator, the thermal separator extending through a thickness of the bond head. A bond head nozzle is coupled to a first side of the bond head, where the bond head nozzle includes one or more nozzle channels extending through a thickness of the bond head nozzle.

公开(公告)号：US20230317675A1

公开(公告)日：2023-10-05

申请号：US17711925

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Michael Baker ,  Zhaozhi Li ,  Feras Eid ,  Pilin Liu ,  Wenhao Li

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L2224/81203 ,  H01L2224/75983 ,  H01L2224/75252

Abstract: Microelectronic die package structures formed according to some embodiments may include a thermal compression bonding (TCB) tool including a pedestal having a convex surface to receive a package substrate, a bond head to compress a die against the package substrate, and a heat source thermally coupled to at least one of the pedestal or the bond head.

公开(公告)号：US20230317630A1

公开(公告)日：2023-10-05

申请号：US17710502

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Wenhao Li ,  Feras Eid ,  Michael Baker ,  Pilin Liu ,  Zhaozhi Li

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13147 ,  H01L2224/81203

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate comprising one or more conductive interconnect structures on a surface of the substrate. One or more support features are on one or more peripheral regions of the surface of the substrate. A first side of a die is coupled to the one or more conductive interconnect structures and is over the one or more support features. A die backside layer is on the second side of the die.