公开(公告)号：US20250140741A1

公开(公告)日：2025-05-01

申请号：US18494023

申请日：2023-10-25

Applicant: Intel Corporation

Inventor： Rajiv Mongia ,  Sagar Suthram ,  Wilfred Gomes ,  Ravindranath Vithal Mahajan ,  Nicolas Butzen

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/467 ,  H01L23/473 ,  H01L23/522 ,  H10B80/00

Abstract: Embodiments of a microelectronic assembly comprise: a first set comprising one or more of first integrated circuit (IC) dies; a second set comprising another one or more of the first IC dies; a plate between, and in direct contact with, the first set and the second set; and a second IC die coupled to the first set, the second set, and the plate. Each IC die comprises a substrate of semiconductor material and an interconnect region including metallization in interlayer dielectric (ILD), the substrate and the interconnect region share a planar interface, and the first IC dies and the second IC die are arranged with the planar interfaces of the first IC dies parallel to each other and orthogonal to the planar interface of the second IC die.

公开(公告)号：US20240154514A1

公开(公告)日：2024-05-09

申请号：US17984183

申请日：2022-11-09

Applicant: Intel Corporation

Inventor： Nicolas Butzen ,  Harish Krishnamurthy ,  Jingshu Yu

IPC: H02M1/00 ,  G06F1/08 ,  G06F1/26 ,  H02M3/04

CPC classification number: H02M1/0012 ,  G06F1/08 ,  G06F1/26 ,  H02M3/04

Abstract: Embodiments herein relate to controlling one or more voltage regulators (VRs) to avoid excessive degradation when a VR increases it current output to supply a hot spot in a compute domain. In one approach, a group of VRs supply current to the domain and each VR's load is monitored to detect an increase in current. A digital controller can reduce the target voltage and/or switching frequency for a VR experiencing an increase in current to equalize the current outputs among the VRs, within a tolerance. In another aspect, a double control loop is used to control a VR. An inner control loop regulates the output of the VR relative to a target voltage and an outer control loop detects the load and adjusts the target voltage and/or switching frequency to avoid excessive degradation.

公开(公告)号：US20230110239A1

公开(公告)日：2023-04-13

申请号：US17484961

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Nicolas Butzen

IPC: G05F1/575 ,  H02M3/07 ,  G05F3/16

Abstract: Techniques and mechanisms for generating an output voltage with a switched capacitor voltage converter (SCVR). In an embodiment, the SCVR comprises converter cores which are coupled in parallel via multiple buses including a first bus, which is to receive an input voltage, and a second bus with which the SCVR is to provide the output voltage based on the input voltage. A first converter core comprises a capacitor and a first hierarchical switch network (HSN) which is coupled between the capacitor and the multiple buses. The first HSN switchedly provides any of multiple conductive paths each between the capacitor and a different respective one of the multiple buses. Two or more of the conductive paths are each provided with at least one same switch circuit of the first HSN. In another embodiment, the first converter core comprises two HSNs which each have a respective branching tree topology.

公开(公告)号：US20250103074A1

公开(公告)日：2025-03-27

申请号：US18474147

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Harish K. Krishnamurthy ,  Nicolas Butzen ,  Khondker Ahmed ,  Nachiket Desai ,  Su Hwan Kim ,  Krishnan Ravichandran ,  Kaladhar Radhakrishnan ,  Jonathan Douglas

IPC: G05F1/56

Abstract: Embodiments herein relate to a voltage regular (VR) formed from dies stacked on a package base layer. The VR can include a first part on a first die and a second part on a second die, where the different parts are selected based on characteristics of the respective die such as their voltage domains or technologies. In a capacitor-based VR, an input capacitor and switches subject to a relatively high input voltage can be provided in the first die, while a flying capacitor, output capacitor and switches subject to a relatively low output voltage can be provided in the second die. In an inductor-based VR, an inductor and one or more switches subject to a relatively high input voltage can be provided in the first die, while an output capacitor subject to a relatively low output voltage can be provided in the second die.

公开(公告)号：US12166414B2

公开(公告)日：2024-12-10

申请号：US17711461

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Tamir Salus ,  Nicolas Butzen ,  Arvind Raghavan ,  Harish Krishnamurthy

IPC: H02M3/07 ,  G01R19/25

Abstract: Techniques and mechanisms for determining a mode of operation of a switched capacitor voltage regulator (SCVR). In an embodiment, a controller supports multiple modes of operation of the SCVR, wherein the modes each correspond to a different respective sequence of switch states of a converter core of the SCVR. One of the modes is to provide boost voltage regulation with the SCVR. The controller transitions seamlessly and autonomously between two modes based on respective reference switch states of the two modes. In another embodiment, a mode transition is performed based on a signal which a control sensor generates based on a rate of switch events of the voltage regulator, and predetermined reference information indicating current characteristics of the voltage regulator.

公开(公告)号：US20230318448A1

公开(公告)日：2023-10-05

申请号：US17711461

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Tamir Salus ,  Nicolas Butzen ,  Arvind Raghavan ,  Harish Krishnamurthy

IPC: H02M3/07 ,  G01R19/25

CPC classification number: H02M3/07 ,  G01R19/25

Abstract: Techniques and mechanisms for determining a mode of operation of a switched capacitor voltage regulator (SCVR). In an embodiment, a controller supports multiple modes of operation of the SCVR, wherein the modes each correspond to a different respective sequence of switch states of a converter core of the SCVR. One of the modes is to provide boost voltage regulation with the SCVR. The controller transitions seamlessly and autonomously between two modes based on respective reference switch states of the two modes. In another embodiment, a mode transition is performed based on a signal which a control sensor generates based on a rate of switch events of the voltage regulator, and predetermined reference information indicating current characteristics of the voltage regulator.

公开(公告)号：US20250113503A1

公开(公告)日：2025-04-03

申请号：US18478840

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Nicolas Butzen ,  Harish K. Krishnamurthy ,  Khondker Ahmed ,  Nachiket Desai ,  Su Hwan Kim ,  Krishnan Ravichandran ,  Kaladhar Radhakrishnan ,  Jonathan Douglas

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Embodiments herein relate to techniques to integrate a capacitive voltage regulator in an integrated circuit (IC) package. The voltage regulator may provide a power supply to one or more load domains in the IC package. The transistors of the voltage regulator may be included on the same die as one or more of the load domains, another die, and/or an interposer of the IC package. The capacitors may be included in the same die as the transistors, in the interposer, in a package layer (e.g., package core), and/or in the same die as one or more of the load domains. Accordingly, the voltage regulator can be integrated close to the relevant load domains, delivering power with short current paths and thereby providing reduced input impedance, output impedance, and associated losses compared with prior techniques. Other embodiments may be described and claimed.

公开(公告)号：US20250105144A1

公开(公告)日：2025-03-27

申请号：US18474160

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Su Hwan Kim ,  Harish K. Krishnamurthy ,  Nachiket Desai ,  Khondker Ahmed ,  Nicolas Butzen ,  Krishnan Ravichandran ,  Kaladhar Radhakrishnan

IPC: H01L23/522 ,  H01L23/498 ,  H01L25/065 ,  H02M3/335

Abstract: Embodiments herein relate to a voltage regular (VR) formed from die stacked on a package base layer. The die can include a load die stacked on a VR die, with an intermediate layer between the two dies. The VR can include an inductor or transformer as a charge transfer component formed between the dies. For example, the inductor or transformer windings can wind around the intermediate layer and include portions of top metal layers of the VR and load die, where the load die is inverted in the stack. The intermediate layer can be magnetic or non-magnetic for an inductor, or magnetic for a transformer. The VR can optionally be divided among two dies. The VR die may have a gallium nitride substrate to handle a higher input voltage, while the load die comprises a silicon substrate.

公开(公告)号：US20250096200A1

公开(公告)日：2025-03-20

申请号：US18469201

申请日：2023-09-18

Applicant: Intel Corporation

Inventor： Nicolas Butzen ,  Harish K. Krishnamurthy

IPC: H01L25/065 ,  H01L25/18 ,  H02M3/158

Abstract: Embodiments herein relate to a voltage regular (VR) formed by components which are distributed over a stack of dice or wafers. Separate VRs can be provided in separate dice or wafers, where their outputs are coupled at an output path. A common control circuit can be used to control each VR. Passive components of a VR can be distributed on separate dice. For example, capacitors or inductors on the different dice or wafers can be coupled in parallel or in series, respectively. The stack can include dice or wafers of different types, such as silicon and Gallium Nitride. A first VR on a first type of die or wafer can be arranged in cascade with a second VR on a second type of die or wafer. The components in the different dice or wafers can be coupled by vias such as through-silicon vias.

公开(公告)号：US20250103075A1

公开(公告)日：2025-03-27

申请号：US18474156

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Khondker Ahmed ,  Nicolas Butzen ,  Nachiket Desai ,  Su Hwan Kim ,  Harish K. Krishnamurthy ,  Krishnan Ravichandran ,  Kaladhar Radhakrishnan ,  Jonathan Douglas

IPC: G05F1/56

Abstract: Embodiments herein relate to a stacked semiconductor structure which includes a first voltage regulator (VR), external to a package, for supplying current to a compute die in the package. When the required current exceeds a threshold, an additional current source is activated. The additional current source can include a second VR, also external to the package, for supplying current to an integrated voltage regulator (IVR) in the package. The IVR performs voltage down conversion and current multiplication to output a portion of the required current above the threshold, while the output of the first VR is capped at the threshold.