公开(公告)号：US09691711B2

公开(公告)日：2017-06-27

申请号：US15055120

申请日：2016-02-26

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  John S. Guzek ,  Adel A. Elsherbini ,  Nitin Ashok Deshpande

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/568 ,  H01L24/16 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/81

Abstract: An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a mold compound is formed over a semiconductor die, the die being over a front side redistribution layer on a side opposite the mold compound, the redistribution layer extending past the die and the mold compound extending around the die to contact the redistribution layer. A plurality of vias are formed in the mold compound vertically toward the redistribution layer, the vias being outside of the die, wherein the bottoms of the vias are over a ground layer of the front side redistribution layer. A continuous conductive shielding film is applied over the mold compound and into the vias, wherein the shielding film in some of the vias directly connects to the ground layer and wherein the shielding film in some of the vias does not directly connect to the ground layer, the redistribution layer connecting the metal film to an external ground so that the vias form a shield.

公开(公告)号：US20250105207A1

公开(公告)日：2025-03-27

申请号：US18473046

申请日：2023-09-22

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Ashok Deshpande ,  Dimitrios Antartis ,  Gwang-Soo Kim ,  Shawna Marie Liff

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: Systems, apparatus, and articles of manufacture are disclosed to enable integrated circuit packages with double hybrid bonded dies and methods of manufacturing the same include an integrated circuit (IC) package including a first semiconductor die including first metal vias spaced apart along a first layer of a first dielectric material, the first metal vias connected to respective first metal pads of the first semiconductor die, a second semiconductor die including second metal pads of the second semiconductor die, and a hybrid bond layer including a third dielectric material and third metal vias spaced apart along the third dielectric material, a subset of the third metal vias electrically coupling ones of the first metal pads to respective ones of the second metal pads, a first one of the third metal vias positioned beyond a lateral side of the first semiconductor die.

公开(公告)号：US20240347590A1

公开(公告)日：2024-10-17

申请号：US18755306

申请日：2024-06-26

Applicant: Intel Corporation

Inventor： Bhaskar Jyoti Krishnatreya ,  Guruprasad Arakere ,  Nitin Ashok Deshpande ,  Mohammad Enamul Kabir ,  Omkar Gopalkrishna Karhade ,  Keith Edward Zawadzki ,  Trianggono S. Widodo

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L29/0657 ,  H01L21/78 ,  H01L23/562 ,  H01L25/0655 ,  H01L21/30625 ,  H01L21/3065 ,  H01L24/08 ,  H01L2224/08221

Abstract: Systems, apparatus, articles of manufacture, and methods to reduce stress in integrated circuit packages are disclosed. An example semiconductor chip includes: a front surface; a back surface opposite the front surface; a first lateral surface extending between the front surface and the back surface; a second lateral surface extending between the front surface and the back surface; and a curved fillet at an intersection between the first lateral surface and the second lateral surface.

公开(公告)号：US20160181207A1

公开(公告)日：2016-06-23

申请号：US15055120

申请日：2016-02-26

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  John S. Guzek ,  Adel A. Elsherbini ,  Nitin Ashok Deshpande

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/568 ,  H01L24/16 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/81

Abstract: An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a mold compound is formed over a semiconductor die, the die being over a front side redistribution layer on a side opposite the mold compound, the redistribution layer extending past the die and the mold compound extending around the die to contact the redistribution layer. A plurality of vias are formed in the mold compound vertically toward the redistribution layer, the vias being outside of the die, wherein the bottoms of the vias are over a ground layer of the front side redistribution layer. A continuous conductive shielding film is applied over the mold compound and into the vias, wherein the shielding film in some of the vias directly connects to the ground layer and wherein the shielding film in some of the vias does not directly connect to the ground layer, the redistribution layer connecting the metal film to an external ground so that the vias form a shield.

Abstract translation: 半导体芯片封装描述了电磁干扰屏蔽。 在一些实施例中，在半导体管芯上形成模具化合物，模具位于与模具化合物相对的一侧上的正面再分配层上，再分配层延伸超过模具，并且模具化合物围绕模具延伸以接触再分布 层。 多个通孔在模具化合物中垂直地朝向再分布层形成，通孔在模具外部，其中通孔的底部在正面再分布层的接地层之上。 将连续导电屏蔽膜施加到模具化合物上并穿过通孔，其中一些通孔中的屏蔽膜直接连接到接地层，并且其中一些通孔中的屏蔽膜不直接连接到接地层， 再分配层将金属膜连接到外部地面，使得通孔形成屏蔽。