公开(公告)号：US12051698B2

公开(公告)日：2024-07-30

申请号：US17030350

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Daniel G. Ouellette ,  Daniel B. O'Brien ,  Jeffrey S. Leib ,  Orb Acton ,  Lukas Baumgartel ,  Dan S. Lavric ,  Dax M. Crum ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L27/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/775

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/408 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.

公开(公告)号：US11996408B2

公开(公告)日：2024-05-28

申请号：US17726412

申请日：2022-04-21

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Anh Phan ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Stephanie A. Bojarski ,  Gilbert Dewey ,  Orb Acton ,  Willy Rachmady

IPC: H01L27/088 ,  H01L21/762 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/76283 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/4232 ,  H01L29/785

Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

公开(公告)号：US11348916B2

公开(公告)日：2022-05-31

申请号：US16024076

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Anh Phan ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Stephanie A. Bojarski ,  Gilbert Dewey ,  Orb Acton ,  Willy Rachmady

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L21/762 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

公开(公告)号：US11476334B2

公开(公告)日：2022-10-18

申请号：US16957055

申请日：2018-02-08

Applicant: Intel Corporation

Inventor： Orb Acton ,  Joseph Steigerwald ,  Anand Murthy ,  Scott Maddox ,  Jenny Hu

IPC: H01L29/10 ,  H01L21/28 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Techniques and mechanisms for providing functionality of a transistor which comprises a conformal layer of a gate work function silicide. In an embodiment, the transistor comprises a channel region and a gate dielectric which extends and adjoins the channel region. The gate dielectric also adjoins a layer structure of the transistor, the layer structure comprising a silicide. The silicide includes silicon and a component D which comprises a non-metal element from one of Groups IIIa, IVa, or Va. In another embodiment, the silicide further comprises a component M which includes a transition metal element from one of Groups IVb, Vb, VIb, VIIB, or VIIIb and/or which includes a metal element from one of Groups IIIa, IVa, or Va.

公开(公告)号：US20220199472A1

公开(公告)日：2022-06-23

申请号：US17132995

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Robin Chao ,  Bishwajeet Guha ,  Brian Greene ,  Chung-Hsun Lin ,  Curtis Tsai ,  Orb Acton

IPC: H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L21/84

Abstract: Integrated circuitry comprising high voltage (HV) and low voltage (LV) ribbon or wire (RoW) transistor stack structures. In some examples, a gate electrode of the HV and LV transistor stack structures may include the same work function metal. A metal oxide may be deposited around one or more channels of the HV transistor stack, thereby altering the dipole properties of the gate insulator stack from those of the LV transistor stack structure.

公开(公告)号：US20200343343A1

公开(公告)日：2020-10-29

申请号：US16957055

申请日：2018-02-08

Applicant: Intel Corporation

Inventor： Orb Acton ,  Joseph Steigerwald ,  Anand Murthy ,  Scott Maddox ,  Jenny Hu

IPC: H01L29/10 ,  H01L29/49 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: Techniques and mechanisms for providing functionality of a transistor which comprises a conformal layer of a gate work function silicide. In an embodiment, the transistor comprises a channel region and a gate dielectric which extends and adjoins the channel region. The gate dielectric also adjoins a layer structure of the transistor, the layer structure comprising a silicide. The silicide includes silicon and a component D which comprises a non-metal element from one of Groups IIIa, IVa, or Va. In another embodiment, the silicide further comprises a component M which includes a transition metal element from one of Groups IVb, Vb, VIb, VIIB, or VIIIb and/or which includes a metal element from one of Groups IIIa, IVa, or Va.

公开(公告)号：US20250113598A1

公开(公告)日：2025-04-03

申请号：US18375314

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Dan Lavric ,  Jubin Nathawat ,  Orb Acton ,  Michal Mleczko ,  Owen Loh ,  Michael L. Hattendorf

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51

Abstract: An integrated circuit (IC) device includes n- and p-type transistors with and without threshold voltage shifts using a common dopant material in a gate dielectric. The IC device includes at least four threshold voltage for each of n- and p-type transistors. Besides volumeless doping of gate dielectrics, work function metals are used in both n- and p-type transistors. A single dipole dopant may be concurrently introduced into and through similar gate dielectrics in both n- and p-type transistors to achieve consistent threshold voltage shifts with minimal process variation.

公开(公告)号：US20240290788A1

公开(公告)日：2024-08-29

申请号：US18175591

申请日：2023-02-28

Applicant: Intel Corporation

Inventor： Guowei Xu ,  Tao Chu ,  Chiao-Ti Huang ,  Robin Chao ,  David Towner ,  Orb Acton ,  Omair Saadat ,  Feng Zhang ,  Dax M. Crum ,  Yang Zhang ,  Biswajeet Guha ,  Oleg Golonzka ,  Anand S. Murthy

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

Abstract: A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.