公开(公告)号：US20230271445A1

公开(公告)日：2023-08-31

申请号：US17680839

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Wenhao Li ,  Jiraporn Seangatith ,  Paul Diglio ,  Xavier Brun

IPC: B41N1/24

CPC classification number: B41N1/248

Abstract: Reusable composite stencils for spray processes, particularly for spray processes used in the fabrication of integrated circuit devices, may be fabricated having a permanent core and at least one sacrificial material layer. Thus, in operation, when a predetermined amount of the sacrificial material layer has been ablated away by a material being sprayed in the spray process, the remaining sacrificial material layer may be removed and reapplied to its original thickness. Therefore, the permanent core, which is usually expensive and/or difficult to fabricate, may be repeatedly reused.

公开(公告)号：US20210407884A1

公开(公告)日：2021-12-30

申请号：US16912432

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Xavier Brun ,  Paul Diglio ,  Joe Walczyk ,  Sergio Antonio Chan Arguedas

IPC: H01L23/373 ,  B33Y80/00 ,  B33Y70/00

Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof.

公开(公告)号：US20230285999A1

公开(公告)日：2023-09-14

申请号：US17694302

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Wenhao Li ,  Feras Eid ,  Paul Diglio ,  Jiraporn Seangatith

IPC: B05B7/14 ,  B05B7/16

CPC classification number: B05B7/1486 ,  B05B7/1626

Abstract: Cold-spray nozzles, systems, and techniques are described herein related to manufacturing implementations of efficient film deposition. A deposition system includes multiple feed systems to deliver solid powder materials at controlled feed rates and temperatures, and a nozzle, including convergent and divergent sections and connections to the feed systems, to receive a carrier fluid in the convergent section and to spray the carrier fluid and the solid powder materials out of the divergent section. A nozzle includes multiple ports to receive solid powder materials for admission into a carrier fluid, with one or more ports in the convergent section and one or more ports in the divergent section. A method may include delivering a carrier fluid to a nozzle, heating multiple solid powder materials, delivering these solid powder materials to the nozzle, and spraying the solid powder materials out of a divergent section of the nozzle.

公开(公告)号：US20210407877A1

公开(公告)日：2021-12-30

申请号：US16911820

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Joe Walczyk ,  Paul Diglio

IPC: H01L23/31 ,  H01L25/18 ,  H01L25/065 ,  H01L21/56

Abstract: A contiguous integrated heat spreader suitable for an integrated circuit (IC) die package. Heat spreader material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of an IC die, and over a portion of a package substrate beyond an edge of the IC die. The contiguous heat spreader may have high thermal conductivity and offer low thermal resistance in absence of any intervening thermal interface material (TIM). The contiguous heat spreader may span multiple IC die and accommodate different die heights. The heat spreader may be contiguous with multiple die. Heat spreader material may be absent where thermal breaks within the heat spreader are advantageous.

公开(公告)号：US12136577B2

公开(公告)日：2024-11-05

申请号：US16911820

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Joe Walczyk ,  Paul Diglio

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/18

Abstract: A contiguous integrated heat spreader suitable for an integrated circuit (IC) die package. Heat spreader material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of an IC die, and over a portion of a package substrate beyond an edge of the IC die. The contiguous heat spreader may have high thermal conductivity and offer low thermal resistance in absence of any intervening thermal interface material (TIM). The contiguous heat spreader may span multiple IC die and accommodate different die heights. The heat spreader may be contiguous with multiple die. Heat spreader material may be absent where thermal breaks within the heat spreader are advantageous.

公开(公告)号：US12080620B2

公开(公告)日：2024-09-03

申请号：US16912432

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Xavier Brun ,  Paul Diglio ,  Joe Walczyk ,  Sergio Antonio Chan Arguedas

IPC: H01L23/373 ,  B33Y70/00 ,  B33Y80/00

CPC classification number: H01L23/3735 ,  B33Y70/00 ,  B33Y80/00

Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof.

公开(公告)号：US12000487B2

公开(公告)日：2024-06-04

申请号：US17895104

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Paul Diglio ,  Craig Yost ,  Christopher Wade Ackerman

IPC: F16J15/328

CPC classification number: F16J15/328

Abstract: The present disclosure is directed to a system having a first loading component and a second loading component for applying load to a device during a test of the device, the first loading component is configured to be moveable with respect to the second loading component. The system includes a seal member arranged between the first loading component and the second loading component, the seal member is adapted to engage the device during testing so as to apply a load against the device during testing and provide sealing around a cavity positioned below the first loading component and above the device.

公开(公告)号：US20230317549A1

公开(公告)日：2023-10-05

申请号：US17709064

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Wenhao Li ,  Paul Diglio ,  Xavier Brun ,  Johanna Swan

IPC: H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3733 ,  H01L21/4871

Abstract: A porous mesh structure for use in the thermal management of integrated circuit devices may be formed as a solid matrix with a plurality of pores dispersed therein, wherein the solid matrix may be a plurality of fused matrix material particles and the plurality of pores may comprise between about 10% and 90% of a volume of the porous mesh structure. The porous mesh structure may be formed on an integrated circuit device and/or on a heat dissipation assembly component, and may be incorporated into an immersion cooling assembly, wherein the porous mesh structure may act as a nucleation site for a working fluid in the immersion cooling assembly.

公开(公告)号：US11762157B2

公开(公告)日：2023-09-19

申请号：US17482485

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Sufi Ahmed ,  Vineeth Abraham ,  Eric Moret ,  Paul Diglio

IPC: G02B6/42 ,  G02B6/36 ,  G02B6/38

CPC classification number: G02B6/4239 ,  G02B6/3636 ,  G02B6/3839

Abstract: The present disclosure relates to a method including arranging multiple optical fibers between a die and a lid, wherein the die is bent and comprises multiple grooves, each optical fiber in or close to a separate groove; bonding the lid to the die to hold the multiple optical fibers in place in the multiple grooves, wherein the bonding comprises applying a bonding force non-uniformly across the lid to conform the lid to the bent die. A corresponding system is also disclosed herein.

公开(公告)号：US11073538B2

公开(公告)日：2021-07-27

申请号：US15861597

申请日：2018-01-03

Applicant: Intel Corporation

Inventor： Paul Diglio ,  Joe Walczyk

IPC: G01R1/073 ,  G01R1/067 ,  H01L21/00

Abstract: An electrical-test apparatus is provided, which includes a plurality of tester interconnect structures cantilevered from a first side of a substrate. A base may be coupled to a second side of the substrate via one or more interconnect layers. The tester interconnect structures may contact corresponding interconnect structures of a device under test (DUT). In an example, the substrate is laterally movable relative to the DUT along a plane of the substrate, upon contact between the tester interconnect structures and the interconnect structures of the DUT.