公开(公告)号：US20200279349A1

公开(公告)日：2020-09-03

申请号：US16880338

申请日：2020-05-21

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajikshore Barik ,  Nicolas C. Galoppo Von Borries

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  H03M7/30 ,  G06K9/62 ,  G06F9/48 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06T1/60 ,  G06T15/00

Abstract: An apparatus to facilitate processing of a sparse matrix is disclosed. The apparatus includes a plurality of processing units each comprising one or more processing elements, including logic to read operands, a multiplication unit to multiply two or more operands and a scheduler to identify operands having a zero value and prevent scheduling of the operands having the zero value at the multiplication unit.

公开(公告)号：US10706498B2

公开(公告)日：2020-07-07

申请号：US16417132

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajikshore Barik ,  Nicolas C. Galoppo Von Borries

IPC: G06F17/16 ,  H03M7/30 ,  G06K9/62 ,  G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06F9/48 ,  G06N3/04 ,  G06N3/08 ,  G06T1/60 ,  G06T15/00

Abstract: An apparatus to facilitate processing of a sparse matrix is disclosed. The apparatus includes a plurality of processing units each comprising one or more processing elements, including logic to read operands, a multiplication unit to multiply two or more operands and a scheduler to identify operands having a zero value and prevent scheduling of the operands having the zero value at the multiplication unit.

公开(公告)号：US11164281B2

公开(公告)日：2021-11-02

申请号：US16880338

申请日：2020-05-21

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajikshore Barik ,  Nicolas C. Galoppo Von Borries

IPC: G06F17/16 ,  G06T1/20 ,  G06F12/02 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  H03M7/30 ,  G06K9/62 ,  G06N20/00 ,  G06F9/48 ,  G06N3/04 ,  G06N3/08 ,  G06T1/60 ,  G06T15/00

Abstract: An apparatus to facilitate processing of a sparse matrix is disclosed. The apparatus includes a plurality of processing units each comprising one or more processing elements, including logic to read operands, a multiplication unit to multiply two or more operands and a scheduler to identify operands having a zero value and prevent scheduling of the operands having the zero value at the multiplication unit.

公开(公告)号：US20200051203A1

公开(公告)日：2020-02-13

申请号：US16417132

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajikshore Barik ,  Nicolas C. Galoppo Von Borries

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06F9/48 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06T1/60 ,  G06T15/00

Abstract: An apparatus to facilitate processing of a sparse matrix is disclosed. The apparatus includes a plurality of processing units each comprising one or more processing elements, including logic to read operands, a multiplication unit to multiply two or more operands and a scheduler to identify operands having a zero value and prevent scheduling of the operands having the zero value at the multiplication unit.